參數(shù)資料
型號: MC68HC705K1
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: HCMOS Microcontroller Unit
中文描述: HCMOS微控制器
文件頁數(shù): 45/140頁
文件大小: 803K
代理商: MC68HC705K1
Interrupts
Interrupt Types
MC68HC705K1 — Rev. 2.0
TechnicalData
Interrupts
4.3.2.3 IRQ Status and Control Register
The IRQ status and control register (ISCR) contains an external interrupt
mask, an external interrupt flag, and a flag reset bit. Unused bits read as
logic 0s.
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
IRQF — External Interrupt Request Flag
The IRQF bit is a clearable, read-only flag that is set when an external
interrupt request is pending. Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
These conditions set the IRQF bit:
a.
An external interrupt signal on the IRQ/V
PP
pin
An external interrupt signal on pin PA3, PA2, PA1, or PA0
when PA3–PA0 are enabled to serve as external interrupt
sources
b.
The CPU clears the IRQF bit when fetching the interrupt vector.
Writing to the IRQF bit has no effect. Writing a logic 1 to the IRQR bit
clears the IRQF bit.
Address:
$000A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IRQE
0
0
0
IRQF
0
0
Write:
IRQR
Reset:
1
0
0
0
0
0
U
0
= Unimplemented
U = Unaffected
Figure 4-2. IRQ Status and Control Register (ISCR)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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