參數(shù)資料
型號： MC68HC705JB4DWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 81/134頁
文件大?。?/td> 1305K
代理商： MC68HC705JB4DWR2
GENERAL RELEASE SPECIFICATION
February 24, 1999
MOTOROLA
INPUT/OUTPUT PORTS
MC68HC05JB4
7-4
REV 2
NOTE
Enabling or disabling the SLOW edge function does not change the pin
conguration. Reading from an output pin will return the content of the data
register.
7.3.1 Port-B Data Register
7.3.2 Port-B Data Direction Register
SLOWEA
1 =
Enable slow falling-edge output transition feature on PA6 and PA7.
0 =
Disable slow falling-edge output transition feature on PA6 and PA7.
SLOWEB
1 =
Enable slow falling-edge output transition feature on PB0 to PB4.
0 =
Disable slow falling-edge output transition feature on PB0 to PB4.
7.3.3 Port-B Pull-up Control Register
7.4
PORT-C
Port-C is a 6-bit bi-directional port. The port-C data register is at $0002 and the
data direction register (DDRC) is at $0006. Reset does not affect the data regis-
ters, but clears the data direction registers, thereby returning the port pins to
inputs. Writing a ‘one’ to a DDR bit sets the corresponding port bit to output mode.
When the ADON-bit is set, PC4 and PC5 are used as dedicated ADC reference
input, reference high (VRH) and reference low (VRL) respectively. And PC0 to
PC3 can be used as ADC inputs AD0 to AD3 when the appropriate channel is
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PTB
R
0
PB4
PB3
PB2
PB1
PB0
$0001
W
reset:
00000000
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DDRB
R
SLOWEA SLOWEB
0
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
$0005
W
reset:
00000000
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PURB
R
$0011
W
PURB4
PURB3
PURB2
PURB1
PURB0
00000000
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