參數資料
型號： MC68HC705JB4DWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數： 122/134頁
文件大?。?/td> 1305K
代理商： MC68HC705JB4DWR2
GENERAL RELEASE SPECIFICATION
February 24, 1999
MOTOROLA
UNIVERSAL SERIAL BUS MODULE
MC68HC05JB4
10-22
REV 2
T0SEQ — Endpoint 0 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or DATA1) will
be sent during the next IN transaction. Toggling of this bit must be controlled by
software. Reset clears this bit.
1 =
DATA1 Token active for next Endpoint 0 transmit
0 =
DATA0 Token active for next Endpoint 0 transmit
STALL0 — Endpoint 0 Force Stall Bit
This read/write bit causes Endpoint 0 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host Controller. The USB hard-
ware clears this bit when a SETUP token is received. Reset clears this bit.
1 =
Send STALL handshake
0 =
Default
TX0E — Endpoint 0 Transmit Enable
This read/write bit enables a transmit to occur when the USB Host controller
sends an IN token to Endpoint 0. Software should set this bit when data is
ready to be transmitted. It must be cleared by software when no more Endpoint
0 data needs to be transmitted.
If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshake
to any Endpoint 0 IN tokens. Reset clears this bit.
1 =
Data is ready to be sent.
0 =
Data is not ready. Respond with NAK.
RX0E — Endpoint 0 Receive Enable
This read/write bit enables a receive to occur when the USB Host controller
sends an OUT token to Endpoint 0. Software should set this bit when data is
ready to be received. It must be cleared by software when data cannot be
received.
If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake
to any Endpoint 0 OUT tokens. Reset clears this bit.
1 =
Data is ready to be received.
0 =
Not ready for data. Respond with NAK.
TP0SIZ3-TP0SIZ0 — Endpoint 0 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the next IN
token request for Endpoint 0. These bits are cleared by reset.
10.5.5 USB Control Register 1 (UCR1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UCR1
R
T1SEQ
ENDADD
TX1E
FRESUM TP1SZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
$003C
W
reset:
00000000
Figure 10-24. USB Control Register 1 (UCR1)
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