參數(shù)資料
型號: MC68HC705JB2DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDSO20
封裝: SOIC-20
文件頁數(shù): 89/128頁
文件大?。?/td> 2493K
代理商: MC68HC705JB2DW
August 28, 1998
GENERAL RELEASE SPECIFICATION
PROGRAMMABLE TIMER
REV 1.1
9-5
NOTE
To prevent interrupts from occurring between readings of the ACRH
and ACRL, set the I bit in the condition code register (CCR) before
reading ACRH and clear the I bit after reading ACRL.
9.3
INPUT CAPTURE REGISTERS
The input capture function is a technique whereby an external signal (connected
to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is
possible to relate the timing of an external signal to the internal counter value, and
hence to elapsed time.
When the input capture circuitry detects an active edge on the TCAP pin, it
latches the contents of the free-running timer counter registers into the input
capture registers as shown in Figure 9-6.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter
values at successive edges of opposite polarity measures the pulse width of the
signal.
Figure 9-6. Timer Input Capture Block Diagram
The input capture registers are made up of two 8-bit read-only registers (ICRH,
ICRL) as shown in Figure 9-7. The input capture edge detector contains a Schmitt
ICIE
ICRH ($0014)
16-BIT COUNTER
÷ 4
INTERNAL
(fOSC ÷ 2)
TIMER CONTROL REG.
TIMER
REQUEST
INPUT CAPTURE (ICF)
RESET
CLOCK
INTERRUPT
ICRL ($0015)
ICF
TIMER STATUS REG.
$0012
$0013
INTERNAL
($FFFC)
DATA
READ
ICRH
READ
ICRL
LATCH
BUS
IEDG
EDGE
SELECT
& DETECT
LOGIC
IEDG
PB0/TCAP
INTERNAL
DATA
BUS
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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