參數(shù)資料
型號(hào)： MC68HC705JB2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁數(shù)： 103/128頁
文件大?。?/td> 2493K
代理商： MC68HC705JB2DW
GENERAL RELEASE SPECIFICATION
August 28, 1998
UNIVERSAL SERIAL BUS MODULE
MC68HC705JB2
10-8
REV 1.1
Figure 10-8. EOP Transaction Voltage Levels
The width of the SE0 in the EOP is about two bit times. The EOP width is
measured with the same capacitive load used for maximum rise and fall times and
is measured at the same level as the differential signal crossover points of the
data lines.
Figure 10-9. EOP Width Timing
10.2.2 Reset Signaling
A reset is signaled on the bus by the presence of an extended SE0 at the USB
data pins of a device. The reset signaling is specied to be present for a minimum
of 10 ms. An active device (powered and not in the suspend state) seeing a
single-ended zero on its USB data inputs for more than 2.5
s may treat that signal
as a reset, but must have interpreted the signaling as a reset within 5.5
s. For a
Low speed device, an SE0 condition between 4 and 8 low speed bit times
represents a valid USB reset.
A USB sourced reset will hold the MC68HC705JB2 in reset for the duration of the
reset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will be
set after the internal reset is removed (See Section 10.5.2 for more detail).
BUS DRIVEN TO
LAST BIT OF
BUS IDLE
EOP
STROBE
PACKET
IDLE STATE
BUS FLOATS
VOH (min)
VSE (max)
VSE (min)
VOL (min)
VSS
EOP
WIDTH
tPeriod
DIFFERENTIAL
DATA LINES
DATA
CROSSOVER
LEVEL
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)PDF資料
PDF描述
MC68HC705JB2P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP20
MC68HC705JB4P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28
MC68HC705K1CDW 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO16
MC68HC705K1CP 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
MC68HC705K1S 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, CDIP16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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