參數(shù)資料
型號: MC68HC705J2S
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
封裝: WINDOWED, CERDIP-20
文件頁數(shù): 35/82頁
文件大?。?/td> 2545K
代理商: MC68HC705J2S
MEMORY
6-4
Rev. 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
6.1.3 EPROM
Two Kbytes of user EPROM for storage of program instructions and fixed data are
located at addresses $0700–$0EFF. The eight addresses from $0FF8–$0FFF are
EPROM locations reserved for interrupt vectors and reset vectors. Eight additional
EPROM bytes are located at $0FF0–$0FF8. There are two ways to write data to
the EPROM:
The EPROM programming register contains the control bits for programming
the EPROM on a byte-by-byte basis.
The bootloader ROM contains routines to download the contents of an
external memory device to the on-chip EPROM.
6.1.3.1 EPROM Programming
The EPROM programming register, shown in Figure 6-3, contains the control bits
for programming the EPROM.
Figure 6-3. EPROM Programming Register (PROG)
LATCH — EPROM Bus Latch
This read/write bit causes address and data buses to be latched for EPROM
programming. Clearing the LATCH bit automatically clears the EPGM bit.
1 = Address and data buses configured for EPROM programming
0 = Address and data buses configured for normal operation
EPGM — EPROM Programming
This read/write bit applies programming power to the EPROM. To write the
EPGM bit, the LATCH bit must already be set.
1 = EPROM programming power switched on
0 = EPROM programming power switched off
Bits 7–3 and 1 — Not used; always read as zeros.
PROG — EPROM Programming Register
$001C
Bit 7
6
5
4
3
2
1
Bit 0
0
LATCH
0
EPGM
RESET
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)PDF資料
PDF描述
MC68HC705JP7S 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
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MC68HC705SP7CP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
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