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參數(shù)資料
| 型號(hào)： | MC68HC705G1FU |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 93/124頁(yè) |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC705G1FU |
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MOTOROLA
8-4
MC68HC05G1
SERIAL PERIPHERAL INTERFACE
8
Note:
Both the slave device(s) and a master device must be programmed to similar timing
modes for proper data transfer.
When the master device transmits data to a slave via a MOSI line, the slave device responds by
sending data to the master device via the MISO line. This implies full duplex transmission with both
data out and data in synchronized with the same clock signal (one which is provided by the master
device). Thus the byte transmitted is replaced by the byte received and eliminates the need for
separate transmit-empty and receiver-full status bits. A single status bit (SPIF) in the serial
peripheral status register (SPSR, location $2B) is used to signify that the I/O operation is
complete.
Conguration of the MOSI pin is a function of the MSTR bit in the serial peripheral control register
(SPCR, location $2A). When a device is operating as a master, the MOSI pin is an output because
the program in rmware set the MSTR bit as a logic one.
8.2.2
Master In Slave Out (MISO)
The MISO pin is congured as an input in a master (mode) device and as an output pin in a slave
(mode) device. Data is transferred serially from a slave to a master on this line, most signicant
bit rst. The MISO pin of a slave is placed in a high-impedance state if it is not selected by a
master; i.e., its SS pin is a logic one. The timing diagram in Figure 8-2 shows the relationship
between data and serial clock (SCK). As shown in Figure 8-2, four possible timing relationships
may be chosen by using control bits CPOL and CPHA. The master device always allows data to
be applied on the MISO line a half-cycle before the serial clock edge (SCK) in order for the slave
device to latch the data.
Note:
Both the slave device(s) and a master device must be programmed to similar timing
modes for proper data transfer.
When a master device transmits data to a slave device via the MOSI line, the slave device
responds by sending data to the master device via the MISO line. This implies full duplex
transmission with both data out and data in synchronized with the same clock signal (one which
is provided by the master device). Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receiver-full status bits. A single status bit
(SPIF) in the serial peripheral status register (SPSR, location $2B) is used to signify that the I/O
operation is complete.
In the master device, the MSTR control bit in the serial peripheral control register (SPCR, location
$2A) is set to a logic one (by the program) to allow the master device to receive data on its MISO
pin. In the slave device, its MISO pin is enabled by the logic level of the SS pin; i.e., if SS=1 then
the MISO pin is placed in a high impedance state, whereas, if SS=0 the MISO pin is an output for
the slave device.
TPG
66
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC705J1A | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC705J1ACDW | 功能描述:IC MCU 4MHZ 1.2K OTP 20-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤(pán) 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱(chēng):497-9032STM32F101T8U6-ND |
| MC68HC705J1ACP | 功能描述:IC MCU 4MHZ 1.2K OTP 20-DIP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤(pán) 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱(chēng):497-9032STM32F101T8U6-ND |
| MC68HC705J1ACPE | 功能描述:8位微控制器 -MCU HCO5 CORE+1.2K RAM + EPR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC705J2CDW | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:MicroController, 8-Bit, 20 Pin, Plastic, SOP |
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