參數(shù)資料
型號： MC68HC705G1FU
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 52/124頁
文件大?。?/td> 732K
代理商： MC68HC705G1FU
MC68HC05G1
MOTOROLA
4-3
RESETS
4
Table 4-2 shows the internal circuit actions on reset, but not necessary in order of occurrence.
Table 4-2 Reset Action on internal Circuit
DEFAULT CONDITIONS AFTER RESET
1
Timer prescaler resets to zero state.
2
Timer counter congures to $FFFC.
3
Timer output compare (TCMP) bit resets to zero.
4
All timer interrupt enable bits cleared (ICIE, OCIE, and TOIE) to disable timer interrupts.
The OLVL timer bit is also cleared by reset.
5
All data direction registers cleared to zero (default as inputs).
6
Count down register is set to 3.
7
Hours, minutes, and seconds registers are set to zero.
8
Stack pointer congured to $00FF.
9
Internal address bus forced to restart vector ($3FFE-$3FFF).
10
I bit of condition code register set to logic 1.
11
STOP latch cleared.
12
External interrupt latch cleared.
13
WAIT latch cleared.
14
SPI disabled (serial output enable control bit SPE=0).
Other SPI bits cleared are SPIE, MSTR, SPIF, WCOL, and MODF.
15
Serial interrupt enable bit cleared (SPIE).
16
SPI system congured to slave mode.
17
RTC interrupt enable bit is cleared.
Other RTC bits cleared are RTCF, ALF, and SECF.
18
All bits in address $1C, $1D, $24, $25, $26, and $27 are cleared.
19
A/D disabled
20
Watchdog counter reset.
21
Watchdog WDOG bit cleared.
listed numbers do not represent order of occurrence.
TPG
31
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相關代理商/技術參數(shù)
參數(shù)描述
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