參數(shù)資料
型號(hào): MC68HC705G1B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝: SDIP-56
文件頁數(shù): 4/124頁
文件大?。?/td> 732K
代理商: MC68HC705G1B
MC68HC05G1
MOTOROLA
11-3
LOW POWER MODES
11
11.1.1
Programmable Timer during Stop Mode
When the MCU enters Stop mode, the timer counter stops counting (the internal processor clock
is stopped) and remains at that particular count value until the Stop mode is exited by an interrupt,
the counter then resumes counting. If the Stop mode is exited by a reset the counter is forced to
$FFFC. Another feature of the programmable timer in Stop mode, is that if at least one valid input
capture edge occurs at the TCAP pin, the input capture detect circuitry is armed. This action does
not set any timer ags or “wake up” the MCU, but when the MCU does “wake up” there will be an
active input capture ag (and data) from that rst valid edge which occurred during Stop mode. If
the Stop mode is exited by an external reset (logic low on RESET pin), then no such input capture
ag or data action takes place even if there was a valid input capture edge (at the TCAP pin) during
MCU Stop mode.
11.1.2
RTC during Stop Mode
The RTC runs at 32.768KHz. The Stop instruction has no effect on the RTC if the STPOSC bit in
the PLL Status and Control register ($25) is cleared. If the STPOSC bit is set, the RTC stops
operating in Stop mode because the 32.768KHz crystal oscillator is disabled.
11.1.3
SPI during Stop Mode
When the MCU enters Stop mode, the baud rate generator which drives the SPI shuts down. This
essentially stops all master mode SPI operation, thus the master SPI is unable to transmit or
receive any data. If the STOP instruction is executed during an SPI transfer, that transfer is halted
until the MCU exits Stop mode. If Stop mode is exited by a reset, then the appropriate
control/status bits are cleared and the SPI is disabled. If the device is in the slave mode when the
STOP instruction is executed, the slave SPI will still operate. It can still accept data and clock
information in addition to transmitting its own data back to a master device.
At the end of a possible transmission with a slave SPI in Stop mode, no ags are set until a logic
low on IRQ, INT1, or INT2 input results in an MCU “wake-up”. Caution should be observed when
operating the SPI (as slave) during Stop mode because none of the protection circuitry (write
collision, mode fault, etc.) is active.
It should also be noted that when the MCU enters the Stop mode all enabled output drivers (TDO,
TCMP, MISO, MOSI, and SCK ports) remain active and any sourcing from these outputs will be
part of the total supply current required by the device.
See also Section 8.6.
TPG
97
相關(guān)PDF資料
PDF描述
MC68HC705G1FU 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64
MC68HC05G1B 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
MC68HC705JB2DW 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDSO20
MC68HC705JB2P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP20
MC68HC705JB4P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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