參數(shù)資料
型號: MC68HC705G1B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝: SDIP-56
文件頁數(shù): 121/124頁
文件大?。?/td> 732K
代理商: MC68HC705G1B
MOTOROLA
10-12
MC68HC05G1
CPU CORE AND INSTRUCTION SET
10
10.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode byte. Instructions with extended addressing mode are capable of
referencing arguments anywhere in memory with a single three-byte instruction. When using the
Motorola assembler, the user need not specify whether an instruction uses direct or extended
addressing. The assembler automatically selects the short form of the instruction.
EA = (PC+1):(PC+2); PC
← PC+3
Address bus high
← (PC+1); Address bus low ← (PC+2)
10.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in
the 8-bit index register. This addressing mode can access the rst 256 memory locations. These
instructions are only one byte long. This mode is often used to move a pointer through a table or
to hold the address of a frequently referenced RAM or I/O location.
EA = X; PC
← PC+1
Address bus high
← 0; Address bus low ← X
10.3.6
Indexed, 8-bit offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the
operand can be located anywhere within the lowest 511 memory locations. This addressing mode
is useful for selecting the mth element in an n element table.
EA = X+(PC+1); PC
← PC+2
Address bus high
← K; Address bus low ← X+(PC+1)
where K = the carry from the addition of X and (PC+1)
10.3.7
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address
mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola
assembler determines the shortest form of indexed addressing.
EA = X+[(PC+1):(PC+2)]; PC
← PC+3
Address bus high
← (PC+1)+K; Address bus low ← X+(PC+2)
where K = the carry from the addition of X and (PC+2)
TPG
92
相關PDF資料
PDF描述
MC68HC705G1FU 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64
MC68HC05G1B 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
MC68HC705JB2DW 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDSO20
MC68HC705JB2P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP20
MC68HC705JB4P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28
相關代理商/技術參數(shù)
參數(shù)描述
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