參數(shù)資料
型號: MC68HC705C9ACFNE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 81/118頁
文件大?。?/td> 750K
代理商: MC68HC705C9ACFNE
Transmit Data Out (TDO)
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
65
9.12 Transmit Data Out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the output
line. Data format is as discussed in 9.6 Data Format and shown in Figure 9-3. The transmitter generates
a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of
the receiver sample clock.
9.13 SCI I/O Registers
The following I/O registers control and monitor SCI operation:
SCI data register (SCDR)
SCI control register 1 (SCCR1)
SCI control register 2 (SCCR2)
SCI status register (SCSR)
9.13.1 SCI Data Register
The SCI data register (SCDR), shown in Figure 9-8, is the buffer for characters received and for
characters transmitted.
9.13.2 SCI Control Register 1
The SCI control register 1 (SCCR1), shown in Figure 9-9, has these functions:
Stores ninth SCI data bit received and ninth SCI data bit transmitted
Controls SCI character length
Controls SCI wakeup method
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the received character. R8 receives
the ninth bit at the same time that the SCDR receives the other eight bits. Resets have no effect on the
R8 bit.
$0011
Bit 7
6543
2
1
Bit 0
Read:
BIT7
BIT6
BIT55
BIT4
BIT3
BIT2
BIT1
BIT0
Write:
Reset:
Unaffected by reset
Figure 9-8. SCI Data Register (SCDR)
$000E
Bit 7
6543
2
1
Bit 0
Read:
R8
T8
M
WAKE
Write:
Reset:
U
0
U
0
= Unimplemented
U = Undetermined
Figure 9-9. SCI Control Register 1 (SCCR1)
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