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參數(shù)資料
| 型號(hào)： | MC68HC705BS8FB |
| 廠(chǎng)商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 112/128頁(yè) |
| 文件大?。?/td> | 752K |
| 代理商： | MC68HC705BS8FB |
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MOTOROLA
9-8
MC68HC05BS8
SYNC SIGNAL PROCESSOR
9
HDET - Horizontal Sync Signal Detect
1 (set)
–
An active horizontal sync is detected at HSYNC input.
0 (clear) –
No horizontal sync signal at HSYNC input; use internal generated
Hsync for HTTL.
This bit is set when an active horizontal sync signal is detected on the HSYNC pin. If cleared, it
indicates there is no active signal, and the HTTL will output the internally generated Hsync signal.
An active horizontal sync signal is dened as:
HDET=(HSYNC pulse width < 16tCYC) (HSYNC period < 128tCYC) [(H line per frame < 4096) + (VDET=0)]
SOUT - Sync Output Select
1 (set)
–
Use processed VSYNC and HSYNC inputs for VTTL and HTTL.
0 (clear) –
Use internally generated sync signals for VTTL and HTTL.
When cleared, the outputs to VTTL and HTTL are the internally generated signals. When set, the
outputs are the processed input signals. This bit can only be set if both VDET and HDET are logic
1’s, and will be cleared automatically if VDET or HDET is not logic “1”. Reset clears this bit.
INSRT - Hsync Insertion
1 (set)
–
No inserted pulses. HTTL will always follow the HSYNC input.
0 (clear) –
For composite sync inputs, emulated sync pulses will be inserted into
the HTTL signal during the vertical sync pulse.
For separate sync inputs, when this Hsync Insertion bit is cleared, sync pulses will continue to be
the Hsync signal during the vertical sync pulse. For composite sync input, when this bit is cleared,
emulated sync pulses will be inserted into the HTTL during the vertical sync pulse. In both cases,
when this bit is set, there will be no inserted pulses, and HTTL will always follow the HSYNC input.
Reset clears this bit.
SIN1:SIN0 - Sync Input Source
These two bits selects the source of the input sync signals. Reset clears these bits.
SIN1
SIN0
Sync input source
0
Separated sync signal through VSYNC and HSYNC inputs.
0
1
Composite sync signal through HSYNC input.
1
X
Composite sync signal through CSYNC input.
TPG
82
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