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| 型號(hào)： | MC68HC705BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 105/128頁(yè) |
| 文件大?。?/td> | 752K |
| 代理商： | MC68HC705BS8FB |
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MOTOROLA
9-2
MC68HC05BS8
SYNC SIGNAL PROCESSOR
9
9.2
Polarity Correction
The polarity correction block of the sync signal processor accepts the input sync signals and
converts them to negative polarity signals, regardless of the polarity of the inputs. The following
describes the methodologies used in polarity correction.
9.2.1
Separate Vertical Sync Input
To test the polarity of the input sync signal, the duration of the low pulse is examined. If the low
period is longer than a specic value (512
s or 1024t
CYC), as in the case of positive polarity input
sync, the input sync will be inverted before output. For negative polarity input sync signal, it is
anticipated that the duration of the low pulse would be shorter than the specic value, and the input
sync signal passes through to the output without inversion.
This polarity correction is a continuous process, and the error margin is equal to the maximum
permissible sync pulse width specied (512
s or 1024t
CYC). At power-up or system reset,
negative polarity at input is assumed.
9.2.2
Separate Horizontal or Composite Sync Input
Since the input at HSYNC can be either a pure horizontal sync signal or a composite sync signal,
different methodologies are used in polarity correction.
Unlike the polarity correction for VSYNC, both the high pulse and low pulse of the sync signal at
HSYNC are examined. If the pulse, either active high or low, is longer than a certain period (8
s
or 16 tCYC), it will be regarded as a long pulse. If there are 8 consecutive low long pulses, the input
sync signal will be conrmed as a positive polarity sync signal, and will be inverted. If there are 8
consecutive high long pulses, it will be conrmed as a negative polarity sync signal.
The operation of this module is also continuous, and the error margin is equal to the period of the
pre-set number (default is 8) of horizontal sync pulses. At power-up or system reset, negative
polarity at input is assumed.
TPG
76
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