參數(shù)資料
型號： MC68HC681P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 8/88頁
文件大?。?/td> 461K
代理商： MC68HC681P
Introduction
MOTOROLA
MC68HC681 USER’S MANUAL
1-5
1
1.3 INTERRUPT CONTROL LOGIC
The following registers are associated with the interrupt control logic:
Interrupt Mask Register (IMR)
Interrupt Status Register (ISR)
Auxiliary Control Register (ACR)
Interrupt Vector Register (IVR)
Refer to Section 4 Programming and Register Descriptions for more complete
information on these registers.
A single active-low interrupt output (IRQ) can notify the processor that any of eight internal
events has occurred. These eight events are described in the discussion of the interrupt
status register (ISR) in Section 4 Programming and Register Descriptions. Customers
can program the interrupt mask register (IMR) to allow only certain conditions to cause IRQ
to be asserted while the CPU can read the ISR to determine all currently active interrupting
conditions. When an active-low interrupt acknowledge signal (IACK) from the processor is
asserted while the DUART has an interrupt pending, the DUART will place the contents of
the interrupt vector register (IVR) on the data bus and assert the data transfer acknowledge
signal (DTACK). If the DUART has no pending interrupt, it ignores IACK cycles. In addition,
customers can program the parallel outputs OP3 through OP7 to provide discrete interrupt
outputs for the transmitters, the receivers, and the C/T.
1.4 DATA BUS BUFFER
The data bus buffer provides the interface between the external and internal data buses. It
is controlled by the internal control logic to allow read and write data transfer operations to
occur between the controlling CPU and DUART by way of the eight parallel data lines (DO
through D7).
1.5 COMMUNICATION CHANNELS A AND B
Each communication channel comprises a full-duplex asynchronous receiver/transmitter
(UART). The operating frequency for each receiver and each transmitter can be selected
independently from the baud-rate generator, the C/T, or from an external clock. The
transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the
appropriate start, stop, and optional parity bits, and outputs a composite serial stream of
data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this
serial input to parallel format, checks for a start bit, stop bit, parity bit (if any), or break
condition, and transfers an assembled character to the CPU during read operations.
1.6 INPUT PORT
The CPU reads the inputs to this 6-bit port (IP0 through IP5). High or low inputs to the input
port result in the CPU reading a logic one or logic zero, respectively; that is, there is no
inversion of the logic level. Each input port bit also has an alternate control function
capability. The alternate functions can be enabled/disabled on a bit-by-bit basis.
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