參數(shù)資料
型號(hào)： MC68HC681P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 47/88頁(yè)
文件大?。?/td> 461K
代理商： MC68HC681P
Programming and Register Descriptions
MOTOROLA
MC68HC681 USER’S MANUAL
4-21
4
4.3.11.5 OP3 OUTPUT SELECT - OPCR[3:2]. This field programs the parallel output
OP3 to provide one of the following:
4.3.11.6 OP2 OUTPUT SELECT - OPCR[1:0]. This field programs the parallel output
OP2 to provide one of the following:
4.3.12 Output Port Register - OPR[7:0]
These bits contain the complement of the logic levels output at the output port pins (OP7-
OPO). Customers can set these register bits by performing a write to the bit set command
address, with data specifying the bits to be set (one equals set, zero equals no change).
Customers can clear these register bits by performing a write to the bit reset command
address, with data specifying the bits to be cleared (one equals reset, zero equals no
change).
4.3.13 Auxiliary Control Register (ACR)
4.3.13.1 BAUD-RATE GENERATOR SET SELECT - ACR[7]. This bit selects the set of
baud-rate generator outputs available for use by the channel A and B receivers and
transmitters. Baud-rate generator characteristics are given in Table 4-5.
OPCR[3:2]
OP3 FUNCTION
0 0
Complement of OPR[3].
0 1
Counter/timer output, open-collector. In counter mode (ACR[6]=0), OP3 is the complement of ISR[3] (not
masked by the interrupt mask register). In timer mode (ACR[6]=1), this output is a square wave at the
programmed frequency. Because the timer cannot be stopped, OPCR[3:2] should be cleared until the
timer has been programmed for the desired operation.
1 0
1X bit-rate clock of the channel B transmitter, which is the clock that shifts the transmitted data. If data is
not being transmitted, a free-running 1X clock is output.
1 1
1X bit-rate clock of the channel B receiver, which is the clock that samples the received data. If data is not
being received, a free-running 1X clock is output.
OPCR[1:0]
OP2 FUNCTION
0 0
Complement of OPR[2].
0 1
16X bit-rate clock of the channel A transmitter. This is the clock selected by CSRA[3:0] and will be a 1X
clock if CSRA[3:0] = 1 1 1 1.
1 0
1X bit-rate clock of the channel A transmitter, which is the clock that shifts the transmitted data. A free
running 1X clock is always output in this mode. If data is not being transmitted, a free-running 1X clock
is output.
1 1
1X bit-rate clock of the channel A receiver, which is the clock that samples the received data. A free running
1X clock is always output in this mode. If data is not being received, a free-running 1X clock is output.
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