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參數(shù)資料
| 型號(hào)： | MC68HC681P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 39/88頁(yè) |
| 文件大小： | 461K |
| 代理商： | MC68HC681P |
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Programming and Register Descriptions
4-14
MC68HC681 USER’S MANUAL
MOTOROLA
4
4.3.2 Channel A Mode Register 2 (MR2A)
The channel A mode register two (MR2A) is accessed when the channel A mode register
pointer points to MR2, which occurs after any access to channel A mode register one
(MR1A). Accesses to MR2A do not change the pointer.
4.3.2.1 CHANNEL A MODE SELECT - MR2A[7:6]. Each channel of the DUART can
operate in one of four modes: normal, automatic echo, local loopback, or remote
loopback. MR2A[7:6] = 00 is the normal mode, with the transmitter and receiver operating
independently. MR2A[7:6] = 01 places the channel in the automatic echo mode, which
automatically retransmits the received data. The following conditions are true while in the
automatic-echo mode:
Received data is reclocked and retransmitted on the channel A transmitter serial-data
output.
The receive clock is used for the transmitter.
The receiver must be enabled, but the transmitter need not be enabled.
The channel A transmitter ready and transmitter empty status bits are inactive.
The received parity is checked, but is not recalculated for transmission; i.e., the
transmitted parity bit is as received.
Character framing is checked but the stop bits are retransmitted as received.
A received break is echoed as received until the next valid start bit is detected.
CPU-to-receiver communication continues normally, but the CPU-to-transmitter link
is disabled.
Two diagnostic modes can also be configured. MR2A[7:6] = 10 selects the first of these,
the local- loopback mode. In this mode
The transmitter output is internally connected to the receiver input.
The transmit clock is used for the receiver.
The channel A transmitter serial-data output is held high.
The channel A receiver serial-data input is ignored.
The transmitter must be enabled, but the receiver need not be enabled.
CPU-to-transmitter and receiver communications continue normally.
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