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參數(shù)資料
| 型號： | MC68HC681FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 55/88頁 |
| 文件大?。?/td> | 461K |
| 代理商： | MC68HC681FN |
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Electrical Specifications
MOTOROLA
MC68HC681 USER’S MANUAL
5-5
5
5.5.4 Interrupt Bus Cycle Timing
CHARACTERISTIC
SYMBOL
MIN
MAX
UNIT
IACK Setup Time to X1 High 1
tCSC
90
—
ns
R/W Setup Time to IACK Asserted 2
tRWS
10
—
ns
IACK Pulse Width Asserted
tIAWL
205
—
ns
Data Valid from IACK Asserted
tDD
—
175
ns
DTACK Asserted from X1 High
tDCR
—
125
ns
IACK Negated from DTACK Asserted 3
tCSD
0
—
ns
R/W Hold Time from IACK Negated
tRWH
0—
ns
Data Hold Time from IACK Negated
tDH
0
—
ns
Data Bus Floating from IACK Negated
tDF
—
100
ns
DTACK Negated from IACK Negated
tDAH
—
100
ns
DTACK Hi-Z from IACK Negated
tDAT
—
125
ns
NOTES:
1.
This specication is only to ensure DTACK is asserted with respect to the rising edge of X1 as shown in Figure 5-3 and Figure 5-
4, not to guarantee operation of the part. If the setup time is violated, DTACKmay be asserted as shown, or may be asserted one
clock cycle later.
2.
During IACK cycles, the MC68681 ignored R/W; this is not true in the MC68HC681: R/W must be high on IACK cycles. The
MC68HC681 ignores IACK if R/W is low.
3.
This specication is only to ensure that DTACK will be asserted. If IACK is negated before DTACK is asserted, DTACK may not
be asserted.
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