參數(shù)資料
型號(hào)： MC68HC681FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 30/88頁(yè)
文件大?。?/td> 461K
代理商： MC68HC681FN
Programming and Register Descriptions
4-6
MC68HC681 USER’S MANUAL
MOTOROLA
4
Similarly, certain changes to the auxiliary control register (ACR bits six through four)
should only be made while the counter/timer (C/T) is not used (i.e., stopped if in counter
mode, output and/or interrupt masked in timer mode).
Channel A mode registers MR1A and MR2A are accessed via an auxiliary pointer. The
pointer is set to mode register one (MR1A) by RESET or by issuing a "reset pointer"
command via the channel A command register. Any read or write of the mode register
switches the pointer to mode register two (MR2A). All subsequent accesses will address
MR2A unless the pointer is reset to MR1A as described above. The channel B mode
registers MR1B and MR2B are accessed by an identical pointer independent of the
channel A pointer. Mode, command, clock-select, and status registers are duplicated for
each channel to allow independent operation and control (except that both channels are
restricted to baud rates that are in the same set).
4.2 REGISTER BIT FORMATS
Rx RTR—Control
0 = Disabled
1 = Enabled
Rx IRQ = Select
0 = RxRDY
1 = FFULL
Error Mode
0 = Character
1 = Block
Parity Mode (Bits 4 and 3)
0 0 = With Parity
0 1 = Force Parity
1 0 = No Parity
1 1 = Multidrop Mode
Parity Type
With Parity
0 = Even
1 = Odd
Channel A/B Mode Register 1 (MR1A/MR1B)
7
654321
0
RX RTR
RX IRQ
ERROR
MODE
PARITY MODE
PARITY
TYPE
BITS PER CHARACTER
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