參數(shù)資料
型號： MC68HC681FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 41/88頁
文件大?。?/td> 461K
代理商： MC68HC681FN
Programming and Register Descriptions
4-16
MC68HC681 USER’S MANUAL
MOTOROLA
4
4.3.2.3 CHANNEL A CLEAR-TO-SEND CONTROL - MR2A[4]. If this bit is zero,
channel A clear-to-send control (CTSA) has no effect on the transmitter. If this bit is a one,
the transmitter checks the state of CTSA (IP0) each time it is ready to send a character.
If IP0 is asserted (low), the character is transmitted. If it is negated (high), the channel A
transmitter serial-data output remains in the marking state and the transmission is
delayed until CTSA goes low. Changes of CTSA while a character is being transmitted do
not affect the transmission of that character.
4.3.2.4 CHANNEL A STOP BIT LENGTH SELECT - MR2A[3:2]. This field programs
the number of stop bits appended to transmitted characters. One, one-and-a-half (async
mode only), or two stop bits can be programmed for any character length. In all cases,
the receiver checks only for a "mark" condition at the center of the first stop bit position
(one bit time after the last data bit, or after the parity bit if parity is enabled).
4.3.3 Channel B Mode Register 1 (MR1B)
The channel B mode register one (MR1 B) is accessed when the channel B mode register
pointer points to MR1. The pointer is set to MR1 by RESET or by a "set pointer" command
applied via command register B. After reading or writing MR1B, the pointer will point to
channel B mode register two (MR2B). The bit definitions for this register are identical to
the bit definitions for MR1A, except that all control actions apply to the channel B receiver
and transmitter and their corresponding inputs and outputs.
4.3.4 Channel B Mode Register 2 (MR2B)
The channel B mode register two (MR2B) is accessed when the channel B mode register
pointer points to MR2, which occurs after any access to channel B mode register one
(MR1 B). Accesses to MR2B do not change the pointer. The bit definitions for this register
are identical to the bit definitions for MR2A, except that all control actions apply to the
channel B receiver and transmitter and their corresponding inputs and outputs.
4.3.5 Channel A Clock-Select Register (CSRA)
In the paragraphs below, ACR[7] controls the set of available baud rates.
4.3.5.1 CHANNEL A RECEIVER CLOCK SELECT - CSRA[7:4]. This field selects the
baud-rate clock for the channel A receiver from the set of available baud rates. The
receiver clock is always 16 times the baud rate given in the table except for
CSRA[7:4] = 1111, when an external 1X clock is used. When CSRA[7:5] = 111, the
receiver uses the external clock connected to parallel input IP4.
4.3.5.2 CHANNEL A TRANSMITTER CLOCK SELECT - CSRA[3:0]. This field selects
the baud rate clock for the channel A transmitter from the set of available baud rates. The
transmitter clock is always 16 times the baud rate given in the table except for
CSRA[3:0] = 1111, when an external 1X clock is used. When CSRA[3:1] = 111, the
external clock connected to parallel input IP3 is used by the transmitter.
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