參數(shù)資料
型號: MC68HC12BE32MFU8
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 62/362頁
文件大?。?/td> 4604K
代理商: MC68HC12BE32MFU8
Standard Timer Module (TIM)
Data Sheet
M68HC12B Family — Rev. 9.0
154
Standard Timer Module (TIM)
MOTOROLA
TSWAI — Timer Stops While in Wait Bit
Timer interrupts cannot be used to get the MCU out of wait.
0 = Allows timer to continue running during wait
1 = Disables timer when MCU is in wait mode
TSBCK — Timer Stops While in Background Mode Bit
0 = Allows timer to continue running while in background mode
1 = Disables timer when MCU is in background mode; useful for emulation
TFFCA — Timer Fast Flag Clear All Bit
0 = Allows timer flag clearing to function normally
1 = For TFLG1($8E), a read from an input capture or a write to the output
compare channel ($90–$9F) causes the corresponding channel flag,
CnF, to be cleared. For TFLG2 ($8F), any access to the TCNT register
($84, $85) clears the TOF flag. Any access to the PACNT register ($A2
and $A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1).
This has the advantage of eliminating software overhead in a separate
clear sequence.
NOTE:
Extra care is required to avoid accidental flag clearing due to unintended accesses.
12.3.7 Timer Control Registers
Read: Anytime
Write: Anytime
OMn — Output mode
OLn — Output level
These eight pairs of control bits are encoded to specify the output action to be
taken as a result of a successful OCn compare (see Table 12-1). When either
OMn or OLn is 1, the pin associated with OCn becomes an output tied to OCn
regardless of the state of the associated DDRT bit.
Address: $0088
Bit 7
654321
Bit 0
Read:
OM7OL7
OM6OL6
OM5OL5
OM4OL4
Write:
Reset:
00000000
Figure 12-8. Timer Control Register 1 (TCTL1)
Address: $0089
Bit 7
654321
Bit 0
Read:
OM3OL3
OM2OL2
OM1OL1
OM0OL0
Write:
Reset:
00000000
Figure 12-9. Timer Control Register 2 (TCTL2)
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