
MOTOROLA
11-14
MC68HC11PH8
CPU CORE AND INSTRUCTION SET
11
SUBA (opr)
Subtract memory from A
A M
A
A
IMM
A
DIR
A
EXT
A
IND, X
A
IND, Y
80
90
B0
A0
18 A0
ii
dd
hh ll
ff
2
3
4
5
SUBB (opr)
Subtract memory from B
B M
B
B
IMM
B
DIR
B
EXT
B
IND, X
B
IND, Y
C0
D0
F0
E0
18 E0
ii
dd
hh ll
ff
2
3
4
5
SUBD (opr)
Subtract memory from D
D M:M+1
D
IMM
DIR
EXT
IND, X
IND, Y
83
93
B3
A3
18 A3
jj
kk
dd
hh ll
ff
4
5
6
7
SWI
Software interrupt
INH
3F
14
1
TAB
Transfer A to B
A
B
INH
16
2
0
TAP
Transfer A to CC register
A
CCR
INH
06
2
↓
TBA
Transfer B to A
B
A
INH
17
2
0
TEST
Test (only in test modes)
address bus increments
INH
00
TPA
Transfer CC register to A
CCR
A
INH
07
2
TST (opr)
Test for zero or minus
M 0
EXT
IND, X
IND, Y
7D
6D
18 6D
hh ll
ff
6
7
00
TSTA
Test A for zero or minus
A 0
A
INH
4D
2
00
TSTB
Test B for zero or minus
B 0
B
INH
5D
2
00
TSX
Transfer stack pointer to X
SP + 1
IX
INH
30
3
TSY
Transfer stack pointer to Y
SP + 1
IY
INH
18 30
4
TXS
Transfer X to stack pointer
IX 1
SP
INH
35
3
TYS
Transfer Y to stack pointer
IY 1
SP
INH
18 35
4
WAI
Wait for interrupt
stack registers & WAIT
INH
3E
à
XGDX
Exchange D with X
IX
D; D IX
INH
8F
3
XGDY
Exchange D with Y
IY
D; D IY
INH
18 8F
4
Operators
Operands
Is transferred to
dd
8-bit direct address ($0000$00FF); the high byte is assumed
Boolean AND
to be zero
+
Arithmetic addition, except where used as an
ff
8-bit positive offset ($00 to $FF (0 to 256)) is added to the
inclusive-OR symbol in Boolean formulae
contents of the index register
⊕ Exclusive-OR
hh
High order byte of 16-bit extended address
*
Multiply
ii
One byte of immediate data
:
Concatenation
jj
High order byte of 16-bit immediate data
Arithmetic subtraction, or negation symbol
kk
Low order byte of 16-bit immediate data
(Twos complement)
ll
Low order byte of 16-bit extended address
mm
8-bit mask (set bits to be affected)
rr
Signed relative offset ($80 to $7F (128 to +127));
offset is relative to the address following the offset byte
Cycles
Condition Codes
Innite, or until reset occurs
Bit not changed
à
12 cycles are used, beginning with the opcode
0
Bit always cleared
fetch. A wait state is entered, which remains
1
Bit always set
in effect for an integer number of MPU E clock
Bit set or cleared, depending on the operation
cycles (n) until an interrupt is recognised.
↓ Bit can be cleared, but cannot become set
Finally, two additional cycles are used to fetch
?
Not dened
the appropriate interrupt vector. (14 + n, total).
Table 11-2 Instruction set (Sheet 6 of 6)
Mnemonic
Operation
Description
Addressing
mode
Instruction
Condition codes
Opcode
Operand
Cycles
S X H
I
N Z V C
TPG
222