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參數(shù)資料
| 型號(hào)： | MC68HC11PH8CFN3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁(yè)數(shù)： | 217/264頁(yè) |
| 文件大?。?/td> | 1484K |
| 代理商： | MC68HC11PH8CFN3 |
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08/Apr/97@13:55 [DS97 v 4.1]
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PH8.DS03/Modes+mem
MOTOROLA
3-10
MC68HC11PH8
OPERATING MODES AND ON-CHIP MEMORY
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3.3
System initialization
Registers and bits that control initialization and the basic operation of the MCU are protected
against writes except under special circumstances. The following table lists registers that can be
written only once after reset, or that must be written within the rst 64 cycles after reset.
3.3.1
Mode selection
The four mode variations are selected by the logic states of the mode A (MODA) and mode B
(MODB) pins during reset. The MODA and MODB logic levels determine the logic state of special
mode (SMOD) and the mode A (MDA) control bits in the highest priority I-bit interrupt and
miscellaneous (HPRIO) register.
After reset is released, the mode select pins no longer inuence the MCU operating mode. In
single chip operating mode, MODA pin is connected to a logic zero. In expanded mode, MODA is
normally connected to VDD through a pull-up resistor of 4.7 k. The MODA pin also functions as
the load instruction register (LIR) pin when the MCU is not in reset. The open-drain active low LIR
output pin drives low during the rst E cycle of each instruction, if enabled by the LIRDV bit in the
OPT2 register. The MODB pin also functions as the stand-by power input (VSTBY), which allows
the RAM contents to be maintained in the absence of VDD.
(1) When SMOD = 0, bits 1 and 0 can be written only once, during the rst 64 cycles, after
which they become read-only. When SMOD = 1, however, these bits can be written at any
time. All other bits can be written at any time.
(2) Bit 0 (LCDE) can be written only once.
(3) Bits can be written to zero once and only in the rst 64 cycles or in special modes. Bits can
be set to one at any time.
(4) Bit 0 (DISE) and bit 1 (EXT4X) can be written only once; bit 4 (IRVNE) can be written only
once in single chip and user expanded modes.
(5) Bits 5, 4, 2, 1, and 0 can be written once and only in the rst 64 cycles; when SMOD = 1,
however, bits 5, 4, 2, 1, and 0 can be written at any time. All other bits can be written at any time.
(6) When SMOD = 0, bits can be written only once, during the rst 64 cycles, after which the
register becomes read-only. When SMOD = 1, bits can be written at any time.
Table 3-3 Registers with limited write access
Register
address
Register
name
Must be written in
rst 64 cycles
Write
once only
$x024
Timer interrupt mask register 2 (TMSK2)
(1)
$x02D
LCD control and data register (LCDR)
No
(2)
$x035
Block protect register (BPROT)
(3)
$x037
EEPROM mapping register (INIT2)
No
Yes
$x038
System conguration options register 2 (OPT2)
No
(4)
$x039
System conguration options register (OPTION)
(5)
$x03D
RAM and I/O map register (INIT)
(6)
TPG
54
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