
MOTOROLA
iv
MC68HC11P2
TABLE OF CONTENTS
Paragraph
Number
Page
Number
Title
5.8.1.1
S2BDH, S2BDL — SCI2/3 baud rate control registers ..............................5-15
5.8.1.2
S2CR1 — SCI2 control register 1 ..............................................................5-15
5.8.1.3
S2CR2 — SCI2 control register 2 ..............................................................5-15
5.8.1.4
S2SR1 — SCI2 status register 1................................................................5-16
5.8.1.5
S2SR2 — SCI2 status register 2................................................................5-16
5.8.1.6
S2DRH, S2DRL — SCI2 data high/low registers.......................................5-16
5.8.2
SCI3.................................................................................................................5-17
5.8.2.1
S3CR1 — SCI3 control register 1 ..............................................................5-17
5.8.2.2
S3CR2 — SCI3 control register 2 ..............................................................5-17
5.8.2.3
S3SR1 — SCI3 status register 1................................................................5-17
5.8.2.4
S3SR2 — SCI3 status register 2................................................................5-18
5.8.2.5
S3DRH, S3DRL — SCI3 data high/low registers.......................................5-18
6
MOTOROLA INTERCONNECT BUS (MI BUS)
6.1
Push-pull sequence ...............................................................................................6-2
6.1.1
The push eld ..................................................................................................6-2
6.1.2
The pull eld ....................................................................................................6-3
6.2
Biphase coding ......................................................................................................6-3
6.3
Message validation................................................................................................6-4
6.3.1
Controller detected errors ................................................................................6-4
6.3.2
MCU detected errors .......................................................................................6-4
6.4
Interfacing to MI BUS ............................................................................................6-6
6.5
MI BUS clock rate ..................................................................................................6-7
6.6
SCI/MI BUS2 registers ..........................................................................................6-8
6.6.1
INIT2 — EEPROM mapping and MI BUS delay register .................................6-8
6.6.2
S2BDH, S2BDL — MI BUS clock rate control registers...................................6-9
6.6.3
S2CR1 — MI BUS2 control register 1 .............................................................6-9
6.6.4
S2CR2 — MI BUS2 control register 2 .............................................................6-10
6.6.5
S2SR1 — MI BUS2 status register 1 ...............................................................6-11
6.6.6
S2SR2 — MI BUS2 status register 2 ...............................................................6-12
6.6.7
S2DRL — MI BUS2 data register ....................................................................6-12
6.7
SCI/MI BUS3 registers ..........................................................................................6-13
6.7.1
S3CR1 — MI BUS3 control register 1 .............................................................6-13
6.7.2
S3CR2 — MI BUS3 control register 2 .............................................................6-13
6.7.3
S3SR1 — MI BUS3 status register 1 ...............................................................6-13
6.7.4
S3SR2 — MI BUS3 status register 2 ...............................................................6-13
6.7.5
S3DRL — MI BUS3 data register ....................................................................6-13