Operating Modes and On-Chip Memory
Technical Data
MC68HC11P2 — Rev 1.0
Operating Modes and On-Chip Memory
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Timer output compare 4 (TOC4) high $001C
Timer output compare 4 (TOC4) low
Capture 4/compare 5 (TI4/O5) high
Capture 4/compare 5 (TI4/O5) low
Timer control 1 (TCTL1)
Timer control 2 (TCTL2)
Timer interrupt mask 1 (TMSK1)
Timer interrupt flag 1 (TFLG1)
Timer interrupt mask 2 (TMSK2)
Timer interrupt flag 2 (TFLG2)
Pulse accumulator control (PACTL)
Pulse accumulator count (PACNT)
SPI control (SPCR)
SPI status (SPSR)
SPI data (SPDR)
(bit 15)
(bit 7)
(bit 15)
(bit 7)
OM2
EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000
OC1I
OC2I
OC3I
OC4I
I4/O5I
OC1F
OC2F
OC3F
OC4F I4/O5F
TOI
RTII
PAOVI
PAII
0
TOF
RTIF
PAOVF
PAIF
0
0
PAEN PAMODPEDGE
0
(bit 7)
(6)
(5)
(4)
(3)
SPIE
SPE
DWOM MSTR
CPOL
SPIF
WCOL
0
MODF
0
(bit 7)
(6)
(5)
(4)
(3)
(14)
(6)
(14)
(6)
OL2
(13)
(5)
(13)
(5)
OM3
(12)
(4)
(12)
(4)
OL3
(11)
(3)
(11)
(3)
OM4
(10)
(2)
(10)
(2)
OL4
(9)
(1)
(9)
(1)
OM5
(bit 8)
(bit 0)
(bit 8)
(bit 0)
OL5
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
IC1I
IC1F
0
0
I4/O5
(2)
CPHA
0
(2)
IC2I
IC2F
PR1
0
RTR1
(1)
SPR1
0
(1)
IC3I
IC3F
PR0
0
RTR0
(bit 0)
SPR0
0
(bit 0)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
undefined
0000 01uu
0000 0000
undefined
EPROM programming (EPROG)
Port pull-up assignment (PPAR)
$002B
MBE
0
ELAT EXCOL EXROW
0
0
EPGM 0000 0000
$002C
0
0
0
0
HPPUE GPPUE FPPUE BPPUE 0000 1111
reserved
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C RBOOT SMOD
$003D
RAM3
PLL control (PLLCR)
Synthesizer program (SYNR)
A/D control & status (ADCTL)
A/D result 1 (ADR1)
A/D result 2 (ADR2)
A/D result 3 (ADR3)
A/D result 4 (ADR4)
Block protect (BPROT)
reserved
EEPROM mapping (INIT2)
System config. options 2 (OPT2)
System config. options 1 (OPTION)
COP timer arm/reset (COPRST)
EEPROM programming (PPROG)
Highest priority interrupt (HPRIO)
RAM & I/O mapping (INIT)
PLLON
SYNX1 SYNX0 SYNY5 SYNY4 SYNY3 SYNY2 SYNY1 SYNY0 0000 1011
CCF
0
SCAN
MULT
CD
(bit 7)
(6)
(5)
(4)
(3)
(bit 7)
(6)
(5)
(4)
(3)
(bit 7)
(6)
(5)
(4)
(3)
(bit 7)
(6)
(5)
(4)
(3)
BULKP
0
BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1011 1111
BCS
AUTO
BWC
VCOT
MCS
LCK
WEN
1010 1000
CC
(2)
(2)
(2)
(2)
CB
(1)
(1)
(1)
(1)
CA
(bit 0)
(bit 0)
(bit 0)
(bit 0)
u0uu uuuu
undefined
undefined
undefined
undefined
EE3
LIRDV CWOM STRCH IRVNE
ADPU
CSEL
(bit 7)
(6)
ODD
EVEN
EE2
EE1
EE0
M3DL1 M3DL0 M2DL1 M2DL0 0000 0000
LSBF
SPR2
0
CME
FCME
CR1
(3)
(2)
(1)
ROW ERASE EELAT EEPGM 0000 0000
PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
RAM0
REG3
REG2
REG1
0
000x 0000
0001 0000
undefined
IRQE
(5)
0
MDA
RAM1
DLY
(4)
BYTE
CR0
(bit 0)
RAM2
REG0 0000 0000
Table 3-2. Register and control bit assignments (Sheet 2 of 4)
Register name
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
F
Freescale Semiconductor, Inc.
n
.