Operating Modes and On-Chip Memory
On-chip memory
MC68HC11P2 — Rev 1.0
Technical Data
Operating Modes and On-Chip Memory
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3.4.2 Registers
In
Table 3-2
, a summary of registers and control bits, the registers are
shown in ascending order within the 128-byte register block. The
addresses shown are for default block mapping ($0000–$007F),
however, the INIT register remaps the block to any 4k page
($x000–$x07F).
Table 3-2. Register and control bit assignments (Sheet 1 of 4)
Register name
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
undefined
Port A data (PORTA)
Data direction A (DDRA)
Data direction B (DDRB)
Data direction F (DDRF)
Port B data (PORTB)
Port F data (PORTF)
Port C data (PORTC)
Data direction C (DDRC)
Port D data (PORTD)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
PA7
DDA7
DDB7
DDF7
PB7
PF7
PC7
DDC7
0
PA6
DDA6
DDB6
DDF6
PB6
PF6
PC6
DDC6
0
PA5
DDA5
DDB5
DDF5
PB5
PF5
PC5
DDC5
PD5
PA4
DDA4
DDB4
DDF4
PB4
PF4
PC4
DDC4
PD4
PA3
DDA3
DDB3
DDF3
PB3
PF3
PC3
DDC3
PD3
PA2
DDA2
DDB2
DDF2
PB2
PF2
PC2
DDC2
PD2
PA1
DDA1
DDB1
DDF1
PB1
PF1
PC1
DDC1
PD1
PA0
DDA0 0000 0000
DDB0 0000 0000
DDF0
0000 0000
PB0
undefined
PF0
undefined
PC0
undefined
DDC0 0000 0000
PD0
undefined
Data direction D (DDRD)
Port E data (PORTE)
Timer compare force (CFORC)
Output compare 1 mask (OC1M)
Output compare 1 data (OC1D)
Timer count (TCNT) high
Timer count (TCNT) low
Timer input capture 1 (TIC1) high
Timer input capture 1 (TIC1) low
Timer input capture 2 (TIC2) high
Timer input capture 2 (TIC2) low
Timer input capture 3 (TIC3) high
Timer input capture 3 (TIC3) low
Timer output compare 1 (TOC1) high
Timer output compare 1 (TOC1) low
Timer output compare 2 (TOC2) high
Timer output compare 2 (TOC2) low
$0009
$000A
$000B
$000C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3
$000D
OC1D7 OC1D6 OC1D5 OC1D4 OC1D3
$000E
(bit 15)
(14)
$000F
(bit 7)
(6)
$0010
(bit 15)
(14)
$0011
(bit 7)
(6)
$0012
(bit 15)
(14)
$0013
(bit 7)
(6)
$0014
(bit 15)
(14)
$0015
(bit 7)
(6)
$0016
(bit 15)
(14)
$0017
(bit 7)
(6)
$0018
(bit 15)
(14)
$0019
(bit 7)
(6)
0
0
DDD5
PE5
FOC3
DDD4
PE4
FOC4
DDD3
PE3
FOC5
DDD2
PE2
0
0
0
(10)
(2)
(10)
(2)
(10)
(2)
(10)
(2)
(10)
(2)
(10)
(2)
DDD1
PE1
0
0
0
(9)
(1)
(9)
(1)
(9)
(1)
(9)
(1)
(9)
(1)
(9)
(1)
DDD0 0000 0000
PE0
undefined
0
0000 0000
0
0000 0000
0
0000 0000
(bit 8)
0000 0000
(bit 0)
0000 0000
(bit 8)
undefined
(bit 0)
undefined
(bit 8)
undefined
(bit 0)
undefined
(bit 8)
undefined
(bit 0)
undefined
(bit 8)
1111 1111
(bit 0)
1111 1111
(bit 8)
1111 1111
(bit 0)
1111 1111
PE7
FOC1
PE6
FOC2
(13)
(5)
(13)
(5)
(13)
(5)
(13)
(5)
(13)
(5)
(13)
(5)
(12)
(4)
(12)
(4)
(12)
(4)
(12)
(4)
(12)
(4)
(12)
(4)
(11)
(3)
(11)
(3)
(11)
(3)
(11)
(3)
(11)
(3)
(11)
(3)
F
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n
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