參數(shù)資料
型號： MC68HC11F1CFN3R2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 138/174頁
文件大?。?/td> 981K
代理商： MC68HC11F1CFN3R2
MOTOROLA
RESETS AND INTERRUPTS
MC68HC11F1
5-4
TECHNICAL DATA
CR[1:0] — COP Timer Rate Select
The internal E clock is first divided by 215 before it enters the COP watchdog system.
These control bits determine a scaling factor for the watchdog timer. Refer to Table 5-
5.1.6 CONFIG Register
P indicates a previously programmed bit. P(L) indicates that the bit resets to the logic
level held in the latch prior to reset, but the function of COP is controlled by DISR in
TEST1 register.
EE[3:0] — EEPROM Mapping Control
Bit 3 — Not implemented
Always reads one
NOCOP — COP System Disable
0 = COP system enabled (forces reset on time-out)
1 = COP system disabled
Bit 1 — Not implemented
Always reads one
EEON — EEPROM Enable
5.2 Effects of Reset
When a reset condition is recognized, the internal registers and control bits are forced
to an initial state. Depending on the cause of the reset and the operating mode, the
reset vector can be fetched from any of six possible locations. Refer to Table 5-2.
These initial states then control on-chip peripheral systems to force them to known
start-up states, as follows:
CONFIG — System Configuration Register
$103F
Bit 7
654321
Bit 0
EE3
EE2
EE1
EE0
—
NOCOP
—
EEON
RESET:
11111
P
1
Single Chip
11111
P(L)
1
Bootstrap
P
P1P1P
Expanded
PPPP
1
P(L)
1
0
Special Test
Table 5-2 Reset Cause, Operating Mode, and Reset Vector
Cause of Reset
Normal Mode Vector
Special Test or Bootstrap
POR or RESET Pin
$FFFE, FFFF
$BFFE, $BFFF
Clock Monitor Failure
$FFFC, FFFD
$BFFC, $BFFD
COP Watchdog Time-out
$FFFA, FFFB
$BFFA, $BFFB
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