MC68L11E9/E20 Analog-to-Digital Converter Characteristics
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
167
10.14 MC68L11E9/E20 Analog-to-Digital Converter Characteristics
Characteristic(1)
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, 750 kHz ≤ E ≤ 2.0 MHz, unless otherwise noted
Parameter(2)
2. Source impedances greater than 10 k
affect accuracy adversely because of input leakage.
Min
Absolute
Max
Unit
Resolution
Number of bits resolved by A/D converter
—
8
—
Bits
Non-linearity
Maximum deviation from the ideal A/D transfer
characteristics
——
±1LSB
Zero error
Difference between the output of an ideal and an
actual for 0 input voltage
——
±1LSB
Full scale error
Difference between the output of an ideal and an
actual A/D for full-scale input voltage
——
±1LSB
Total unadjusted
error
Maximum sum of non-linearity, zero error, and
full-scale error
——
±1/2
LSB
Quantization error
Uncertainty because of converter resolution
—
±1/2
LSB
Absolute accuracy
Difference between the actual input voltage and
the full-scale weighted equivalent of the binary
output code, all error sources included
——
±2LSB
Conversion range
Analog input voltage range
VRL
—
VRH
V
VRH
Maximum analog reference voltage
VRL
—
VDD + 0.1
V
VRL
Minimum analog reference voltage
VSS –0.1
—
VRH
V
VR
Minimum difference between VRH and VRL
3.0
—
V
Conversion time
Total time to perform a single
analog-to-digital conversion:
E clock
Internal RC oscillator
—
32
—
tCYC+ 32
tCYC
s
Monotonicity
Conversion result never decreases with an
increase in input voltage and has no missing
codes
—
Guaranteed
—
Zero input reading
Conversion result when VIn = VRL
00
—
Hex
Full scale reading
Conversion result when VIn = VRH
——
FF
Hex
Sample acquisition
time
Analog input acquisition sampling time:
E clock
Internal RC oscillator
—
12
—
12
tCYC
s
Sample/hold
capacitance
Input capacitance during sample
PE[7:0]
—
20 typical
—
pF
Input leakage
Input leakage on A/D pins
PE[7:0]
VRL, VRH
—
400
1.0
nA
A