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參數(shù)資料
| 型號(hào)： | MC68HC11E20VFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:5.1"; External Width:5.1"; External Depth:3" |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 35/268頁(yè) |
| 文件大小： | 3696K |
| 代理商： | MC68HC11E20VFU2 |
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Operating Modes and On-Chip Memory
Memory Map
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
35
configuration (CONFIG) register, programming calibration data into electrically
erasable, programmable read-only memory (EEPROM), and supporting emulation
and debugging during development.
2.2.4 Bootstrap Mode
When the MCU is reset in special bootstrap mode, a small on-chip read-only
memory (ROM) is enabled at address $BF00–$BFFF. The ROM contains a
bootloader program and a special set of interrupt and reset vectors. The MCU
fetches the reset vector, then executes the bootloader.
Bootstrap mode is a special variation of the single-chip mode. Bootstrap mode
allows special-purpose programs to be entered into internal random-access
memory (RAM). When bootstrap mode is selected at reset, a small bootstrap ROM
becomes present in the memory map. Reset and interrupt vectors are located in
this ROM at $BFC0–$BFFF. The bootstrap ROM contains a small program which
initializes the serial communications interface (SCI) and allows the user to
download a program into on-chip RAM. The size of the downloaded program can
be as large as the size of the on-chip RAM. After a 4-character delay, or after
receiving the character for the highest address in RAM, control passes to the
loaded program at $0000. Refer to
Figure 2-2
,
Figure 2-3
,
Figure 2-4
,
Figure 2-5
,
and
Figure 2-6
.
Use of an external pullup resistor is required when using the SCI transmitter pin
because port D pins are configured for wired-OR operation by the bootloader. In
bootstrap mode, the interrupt vectors are directed to RAM. This allows the use of
interrupts through a jump table. Refer to the application note AN1060 entitled
M68HC11 Bootstrap Mode
, that is included in this data book
.
2.3 Memory Map
The operating mode determines memory mapping and whether external
addresses can be accessed. Refer to
Figure 2-2
,
Figure 2-3
,
Figure 2-4
,
Figure 2-5
, and
Figure 2-6
, which illustrate the memory maps for each of the three
families comprising the M68HC11 E series of MCUs.
Memory locations for on-chip resources are the same for both expanded and
single-chip modes. Control bits in the configuration (CONFIG) register allow
EPROM and EEPROM (if present) to be disabled from the memory map. The RAM
is mapped to $0000 after reset. It can be placed at any 4-Kbyte boundary ($x000)
by writing an appropriate value to the RAM and I/O map register (INIT). The 64-byte
register block is mapped to $1000 after reset and also can be placed at any 4-Kbyte
boundary ($x000) by writing an appropriate value to the INIT register. If RAM and
registers are mapped to the same boundary, the first 64 bytes of RAM will be
inaccessible.
Refer to
Figure 2-7
, which details the MCU register and control bit assignments.
Reset states shown are for single-chip mode only.
F
Freescale Semiconductor, Inc.
n
.
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