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參數(shù)資料
| 型號(hào)： | MC68HC11D3CFN3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 81/138頁(yè) |
| 文件大?。?/td> | 1047K |
| 代理商： | MC68HC11D3CFN3 |
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MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
47
Chapter 4
Resets, Interrupts, and Low-Power Modes
4.1 Introduction
This section describes the internal and external resets and interrupts of the MC68HC711D3 and its two
low power-consumption modes.
4.2 Resets
The microcontroller unit (MCU) can be reset in any of these four ways:
1.
An active-low input to the RESET pin
2.
A power-on reset (POR) function
3.
A clock monitor failure
4.
A computer operating properly (COP) watchdog timer timeout
The RESET input consists mainly of a Schmitt trigger that senses the RESET line logic level.
4.2.1 RESET Pin
To request an external reset, the RESET pin must be held low for at least eight E-clock cycles, or for one
E-clock cycle if no distinction is needed between internal and external resets.
4.2.2 Power-On Reset (POR)
Power-on reset occurs when a positive transition is detected on VDD. This reset is used strictly for power
turn on conditions and should not be used to detect any drop in the power supply voltage. If the external
RESET pin is low at the end of the power-on delay time, the processor remains in the reset condition until
RESET goes high.
4.2.3 Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer that automatically times out unless it is serviced within a specific
time by a program reset sequence. If the COP watchdog timer is allowed to timeout, a reset is generated,
which drives the RESET pin low to reset the MCU and the external system.
In the MC68HC711D3, the COP reset function is enabled out of reset in normal modes. If the user does
not want the COP enabled, he must write a 1 to the NOCOP bit of the configuration control register
(CONFIG) after reset. This bit is writable only once after reset in normal modes (see 2.3.3 Configuration
Control Register for more information). Protected control bits (CR1 and CR0) in the configuration options
register (OPTION) allow the user to select one of the four COP timeout rates. Table 4-1 shows the
relationship between CR1 and CR0 and the COP timeout period for various system clock frequencies.
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