參數(shù)資料
型號(hào): MC68HC11D3CFN3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 138/138頁
文件大小: 1047K
代理商: MC68HC11D3CFN3
Real-Time Interrupt
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
99
PR1 and PR0 — Timer Prescaler Select Bits
Refer to Table 8-4.
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2
enable the corresponding interrupt sources.
8.5.2 Timer Interrupt Flag 2 Register
Bits of the timer interrupt flag 2 register (TFLG2) indicate the occurrence of timer system events. Coupled
with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either
a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to 1 at the end of every RTI period. To clear RTIF, write a byte
to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits 3–0 — Not implemented
Always read 0.
8.5.3 Pulse Accumulator Control Register
Bits RTR1 and RTR0 of the pulse accumulator control register (PACTL) select the rate for the real-time
interrupt system. Bit DDRA3 determines whether port A bit three is an input or an output when used for
general-purpose I/O. The remaining bits control the pulse accumulator.
Address:
$0025
Bit 7
654321
Bit 0
Read:
TOF
RTIF
PAOVF
PAIF
0000
Write:
Reset:
00000000
Figure 8-17. Timer Interrupt Flag 2 Register (TFLG2)
Address:
$0026
Bit 7
654321
Bit 0
Read:
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Write:
Reset:
00000000
Figure 8-18. Pulse Accumulator Control Register (PACTL)
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