SpeciTcations
MC68HC08AZ32
396
Specifications
MOTOROLA
5.0 Volt DC Electrical Characteristics
Charateristic
Symbol
Min
Typ
Max
Unit
Output High Voltage
(I
LOAD
= –2.0 mA) All Ports and EBI pins
Output Low Voltage
(I
LOAD
= 1.6 mA) All Ports and EBI pins
Input High Voltage
All Ports,EBI pins,IRQ
s
, RESET, OSC1
V
OH
V
DD
–0.8
—
—
V
V
OL
—
—
0.4
V
V
IH
0.7 x V
DD
—
V
DD
V
Input Low Voltage
All Ports, EBI pins,IRQ
s
, RESET, OSC1
V
IL
V
SS
—
0.3 x V
DD
V
V
DD
+ V
DDA
Supply Current
Run (see Note 3)
Wait (see Note 4)
Stop (see Note 5)
25
°
C
–40
°
C to +125
°
C
25
°
C with LVI Enabled
–40
°
C to +125
°
C with LVI Enabled
I
DD
—
—
—
—
—
—
24
12
20
50
300
400
28
14
100
150
500
600
mA
mA
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
I/O Ports Hi-Z Leakage Current
I
L
I
IN
—
—
±
1
±
1
Input Current
—
—
Capacitance
Ports (As Input or Output)
C
OUT
C
IN
V
LVII
H
LVI
V
POR
V
PORRST
R
POR
V
HI
—
—
—
—
12
8
pF
Low-Voltage Reset Inhibit
---
4.2
—
V
Low-Voltage Reset Inhibit/Recover Hysteresis
—
200
—
mV
POR ReArm Voltage (see Note 6)
0
—
200
mV
POR Reset Voltage (see Note 7)
0
—
800
mV
POR Rise Time Ramp Rate (see Note 8)
0.02
—
—
V/ms
High COP Disable Voltage (see Note 9)
V
DD
V
DD
+ 2
V
1.V
= 5.0 Vdc
±
0.5v, V
= 0 Vdc, T
= –40
°
C to +85
°
C, unless otherwise noted.
2.Typical values reflect average measurements at midpoint of voltage range, 25
°
C only.
3.Run (Operating) I
measured using external square wave clock source (f
= 8.4 MHz). All inputs 0.2 V from rail.
No dc loads. Less than 100 pF on all outputs. C
= 20 pF on OSC2. All ports configured as inputs. OSC2 capaci-
tance linearly affects run I
. Measured with all modules enabled.
4.Wait I
measured
using external square wave clock source (f
= 8.4 MHz). All inputs 0.2 Vdc from rail. No dc
loads. Less than 100 pF on all outputs, C
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
linearly affects wait I
. Measured with all modules enabled.
5.Stop I
measured with OSC1 = V
.
6.Maximum is highest voltage that POR is guaranteed.
7.Maximum is highest voltage that POR is possible.
8.If minimum V
is not reached before the internal POR reset is released, RST must be driven low externally until
minimum V
is reached.
9.See
Computer Operating Properly Module (COP)
on page 149.
4-specs