Serial Peripheral Interface (SPI)
Data Sheet
MC68HC08AS32A — Rev. 1
226
Serial Peripheral Interface (SPI)
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MOTOROLA
Figure 15-9. Missed Read of Overflow Condition
Figure 15-10. Clearing SPRF When OVRF Interrupt Is Not Enabled
15.6.2 Mode Fault Error
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit (MODFEN
in SPSCR) must be set. Clearing the MODFEN bit does not clear the MODF flag
but does prevent MODF from being set again after MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable
bit (ERRIE in SPSCR) is also set. The SPRF, MODF, and OVRF interrupts share
READ SPDR
READ SPSCR
OVRF
SPRF
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS SET. BYTE 4 IS LOST.
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READ SPDR
READ SPSCR
OVRF
SPRF
BYTE 1
BYTE 2
BYTE 3
BYTE 4
1
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR, CLEARING SPFR BIT.
CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
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SPI RECEIVE
COMPLETE
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Freescale Semiconductor, Inc.
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