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System Integration Module (SIM)
Reset and System Initialization
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
System Integration Module (SIM)
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203
14.3 Reset and System Initialization
The MCU has these reset sources:
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
Each of these resets produces the vector $FFFE–FFFF ($FEFE–FEFF in monitor
mode) and asserts the internal reset signal (IRST). IRST causes all registers to be
returned to their default values and all modules to be returned to their reset states.
An internal reset clears the SIM counter (see
14.4 SIM Counter
), but an external
reset does not. Each of the resets sets a corresponding bit in the SIM reset status
register (SRSR). (See
14.7 SIM Registers
.)
14.3.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for at least the
minimum t
RL
time.
Figure 14-5
shows the relative timing.
Figure 14-5. External Reset Timing
14.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to
allow resetting of external peripherals. The internal reset signal IRST continues to
be asserted for an additional 32 cycles. See
Figure 14-6
. An internal reset can be
caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. See
Figure 14-7
. Note that for LVI or POR resets, the SIM cycles through 4096
CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset
signal then follows the sequence from the falling edge of RST shown in
Figure
14-6
.
The COP reset is asynchronous to the bus clock.
RST
IAB
PC
VECT H
VECT L
CGMOUT
F
Freescale Semiconductor, Inc.
n
.