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參數(shù)資料
| 型號(hào)： | MC68HC05X4CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁(yè)數(shù)： | 76/156頁(yè) |
| 文件大?。?/td> | 3699K |
| 代理商： | MC68HC05X4CDW |
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Modes of Operation and Pin Descriptions
MC68HC05X4 Rev 1.0
Modes of Operation and Pin Descriptions
RESET
This active low input pin is used to reset the MCU. Applying a logic zero
to this pin forces the device to a known start-up state. An external
RC-circuit can be connected to this pin to generate a power-on reset
(POR) if required. In this case, the time constant must be great enough
(minimum 100 ms) to allow the oscillator circuit to stabilise. This input
has an internal Schmitt trigger to improve noise immunity.
PA0–PA7/PB0–PB7
These sixteen I/O lines comprise ports A and B. The state of any pin is
software programmable and all port A and B lines are configured as
inputs at reset.
When the 16-bit programmable timer is enabled (via the TIMEN bit in the
port configuration register) the PB7/TCMP pin is used for the TCMP
output compare function instead of for the port pin. When the current
value of the 16-bit timer counter matches the value held in the output
compare register then the level specified by the OLVL bit in the timer
control register is clocked out to the TCMP pin.
VDDH
This pin provides the high voltage reference output for the CAN bus. The
output voltage is equal to VDD/2.
VSS1
This pin is the ground connection for the input comparator of the CAN bus.
RX0/RX1
These input pins connect the physical bus lines to the input comparator
(receive). When the MCAN is in SLEEP mode, a ‘dominant’ level on
these pins will waken it.
TX0/TX1
These output pins connect the output drivers of the MCAN to the
physical bus lines (transmit).
NOTE:
CAN bus lines. The bus can have one of two complementary values –
‘dominant’ or ‘recessive’. During simultaneous transmission of ‘dominant’
and ‘recessive’ bits the resulting bus value will be ‘dominant’. For example,
with a positive logic wired-AND implementation of the bus, the ‘dominant’
level would correspond to a logic ‘0’, and the ‘recessive’ level to a logic ‘1’.
14-modes
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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