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| 型號(hào)： | MC68HC05SB7 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | MO-150, SSOP-28 |
| 文件頁(yè)數(shù)： | 147/170頁(yè) |
| 文件大?。?/td> | 2161K |
| 代理商： | MC68HC05SB7 |
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GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
PULSE WIDTH MODULATOR
MC68HC05SB7
11-4
REV 2.1
Each PWM channel is enabled by setting the corresponding DAn-E bit in the
MCER, shown in Figure 11-11. With a PWM output enabled, the corresponding
port I/O is tri-stated automatically. Reset clears the four DAn-E bits.
The outputs from four channels PWM system can be inhibited by setting the
PWM_I bit in MCER. This bit can be used as a global pull logic “0” for all the
enabled DA’s line before enter STOP mode. The PWM_I bit is also used to disable
the counter while the PWM is not in use for power saving. Reset clears this bit.
DAn-E — D/A Channel n Enable
1 =
PWM output selected for PWMn/PAn pin.
0 =
Standard I/O selected for PWMn/PAn pin.
PWM_I — PWM Inhibit
1 =
Inhibit all four PWM channels; PWM 10-bit counter also stopped.
0 =
PWM channels not inhibited.
11.3
PWM DURING WAIT MODE
In WAIT mode, the oscillator is running even though the MCU clock is not present,
the PWM outputs are not affected. To reduce power consumption in WAIT mode, it
is recommended to disable the PWM.
11.4
PWM DURING STOP MODE
In STOP mode, the oscillator is stopped asynchronously with PWM operation. As
a consequence, the PWM output will remain at the state at the moment when the
oscillator is stopped. The PWM pin’s output depended on the state of PWM_I bit.
If this bit is clear, it might be at its high or low state at that moment, and it remains
at that state until STOP mode is exited. If the PWM_I bit is set, it will be inhibited
the state of PWM output in the process and pin output will be in logic low state.
After STOP mode is exited, the PWM output resumes its unnished portion of the
stopped cycle if PWM_I bit is clear by software.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MCER
R
PWM_I
000
DA3-E
DA2-E
DA1-E
DA0-E
$002D
W
reset:
00000000
Figure 11-11. MUX Channel Enable Register (MCER)
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