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參數(shù)資料
| 型號(hào)： | MC68HC05SB7 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | MO-150, SSOP-28 |
| 文件頁(yè)數(shù)： | 114/170頁(yè) |
| 文件大?。?/td> | 2161K |
| 代理商： | MC68HC05SB7 |
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GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
LOW POWER MODES
MC68HC05SB7
6-4
REV 2.1
6.2
WAIT MODE
The WAIT instruction puts the MCU in a low power wait mode which consumes
more power than the stop mode. The wait mode and has the following affects on
the MCU:
Enables interrupts by clearing the I bit in the condition code register.
Enables external interrupts by setting the IRQE bit in the IRQ status and
control register.
Stops the CPU clock which drives the address and data buses, but
allows the internal oscillator and its clock to continue to run and drive the
Core Timer, programmable Timer, analog subsystem and SM-Bus.
The WAIT instruction does not affect any other bits, registers or I/O lines.
The following conditions restart the CPU clock and bring the MCU out of the wait
mode:
An external interrupt signal on the IRQ/VPP pin — A high to low
transition on the IRQ/VPP pin loads the program counter with the
contents of locations $1FFA and $1FFB.
A programmable Timer interrupt — A programmable Timer interrupt
driven by an input capture, output compare or timer overow loads the
program counter with the contents of locations $1FF6 and $1FF7.
An SM-Bus interrupt — An SM-Bus interrupt driven by the completion of
transmitted or received 8-bit data loads the program counter with the
contents of locations $1FF4 and $1FF5.
An analog subsystem interrupt — An analog subsystem interrupt driven
by a voltage comparison loads the program counter with the contents of
locations $1FF2 and $1FF3.
A Core Timer interrupt — A Core Timer overow or a real time interrupt
loads the program counter with the contents of locations $1FF0 and
$1FF1.
A COP watchdog reset — A timeout of the COP watchdog resets the
MCU and loads the program counter with the contents of locations
$1FFE and $1FFF. Software can enable real time interrupts so that the
MCU can periodically exit the wait mode to reset the COP watchdog.
External reset — A logic zero on the RESET pin resets the MCU and
loads the program counter with the contents of locations $1FFE and
$1FFF.
6.3
DATA-RETENTION MODE
In the data retention mode, the MCU retains RAM contents and CPU register con-
tents at VDD voltages as low as 2.0 VDC. The data retention feature allows the
MCU to remain in a low power consumption state during which it retains data, but
the CPU cannot execute instructions.
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