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參數(shù)資料
| 型號： | MC68HC05RC18P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 95/126頁 |
| 文件大?。?/td> | 1180K |
| 代理商： | MC68HC05RC18P |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Core Timer
General Release Specification
MC68HC05RC18 — Rev. 2.1
68
Core Timer
Freescale Semiconductor
If the COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU.
The COP remains enabled after execution of the WAIT instruction and
all associated operations apply. If the STOP instruction is disabled,
execution of STOP instruction causes the CPU to enter wait mode just
as if a wait mode instruction had been executed (except that when stop
mode is exited, the COP timer is cleared). Thus, it is recommended that
stop mode be disabled in devices that have the COP enabled, as this will
prevent the COP from being disabled by the STOP instruction.
This COP’s objective is to make it impossible for this device to become
stuck or locked up and to be sure the COP is able to rescue the part from
any situation where it might entrap itself in abnormal or unintended
behavior. This function is a mask option.
8.6 Timer During Wait Mode
The CPU clock halts during wait mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit
wait mode. The COP is always enabled while in user mode.
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