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參數(shù)資料
| 型號： | MC68HC05RC18P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 80/126頁 |
| 文件大?。?/td> | 1180K |
| 代理商： | MC68HC05RC18P |
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Parallel Input/Output (I/O)
MC68HC05RC18 — Rev. 2.1
General Release Specification
Freescale Semiconductor
Parallel Input/Output (I/O)
57
NON-DISCLOSURE
AGREEMENT
REQUIRED
6.5 Port C
Port C is an 8-bit bidirectional port (PC0–PC7) which does not share any
of its pins with other subsystems. The port C data register is at $0002
and the data direction register (DDR) is at $0006. Reset does not affect
the data register, but clears the data direction register, thereby returning
the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port
bit to output mode. Port C pins PC4–PC7 are available only in higher pin
count (>28 pin) packages.
NOTE:
Only four bits of port C are bonded out in 28-pin packages for the
MC68HC05RC18, although port C is truly an 8-bit port. Since pins
PC4–PC7 are unbonded, software should include the code to set their
respective data direction register locations to outputs to avoid floating
inputs.
6.6 Input/Output Programming
Port pins can be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all pins as
inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin.
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