參數(shù)資料
型號(hào): MC68HC05RC18P
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁(yè)數(shù): 111/126頁(yè)
文件大?。?/td> 1180K
代理商: MC68HC05RC18P
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Carrier Modulator Transmitter (CMT)
MC68HC05RC18 Rev. 2.1
General Release Specification
Freescale Semiconductor
Carrier Modulator Transmitter (CMT)
83
NON-DISCLOSURE
AGREEMENT
REQUIRED
BASE — Baseband Enable
1 = Baseband enabled
0 = Baseband disabled
When set, the BASE bit disables the carrier generator and forces the
carrier output high for generation of baseband protocols. When BASE
is clear, the carrier generator is enabled and the carrier output toggles
at the frequency determined by values stored in the carrier data
registers. See 9.5.1 Time Mode. This bit is cleared by reset. This bit
is not double buffered and should not be written to during a
transmission.
MODE — Mode Select
1 = CMT operates in FSK mode.
0 = CMT operates in Time mode.
For a description of CMT operation in time mode, see 9.5.1 Time
Mode. For a description of CMT operation in FSK mode, see 9.5.2
FSK Mode. This bit is cleared by reset. This bit is not double buffered
and should not be written to during a transmission.
IE — Interrupt Enable
1 = CPU interrupt enabled
0 = CPU interrupt disabled
A CPU interrupt will be requested when EOC is set if IE was previously
set. If IE is clear, EOC will not request a CPU interrupt.
MCGEN — Modulator and Carrier Generator Enable
1 = Modulator and carrier generator enabled
0 = Modulator and carrier generator disabled
Setting MCGEN will initialize the carrier generator and modulator and
will enable all clocks. Once enabled, the carrier generator and
modulator will function continuously. When MCGEN is cleared, the
current modulator cycle will be allowed to expire before all carrier and
modulator clocks are disabled (to save power) and the modulator
output is forced low. To prevent spurious operation, the user should
initialize all data and control registers before enabling the system. This
bit is cleared by reset.
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