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參數(shù)資料
| 型號： | MC68HC05RC18FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 64/124頁 |
| 文件大?。?/td> | 457K |
| 代理商： | MC68HC05RC18FN |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts
General Release Specification
MC68HC05RC18 — Rev. 2.0
44
Interrupts
MOTOROLA
The IRQ pin is one source of an external interrupt. All port B pins
(PB0–PB7) act as other external interrupt sources if their interrupt
feature is enabled as specified by the user.
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to
two cases:
1. Falling edge on the IRQ pin
2. Falling edge on any port B pin with interrupt enabled
When edge and level sensitivity is selected for the IRQ interrupt, it is
sensitive to three cases:
1. Low level on the IRQ pin
2. Falling edge on the IRQ pin
3. Falling edge or low level on any port B pin with interrupt enabled
External interrupts can also be masked by setting the EIMSK bit in the
MSCR register of the IR remote timer. See 9.5.4 Modulator Period
Data Registers (MDR1, MDR2, and MDR3) for details. When masked,
any external interrupt received sets the interrupt latch and remains
pending within the interrupt module until the EIMSK bit is cleared, at that
point, the external interrupt will be forwarded to the CPU for processing.
Reset clears the interrupt latch, as will the CPU when it finishes
processing the external interrupt.
4.6.2 External Interrupt Timing
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
the IRQ source. The interrupt request is then synchronized internally and
serviced as specified by the contents of $3FFA and $3FFB.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-
only trigger is available via the mask programmable option for the IRQ
pin.
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