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參數(shù)資料
| 型號： | MC68HC05RC17DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.097 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 93/128頁 |
| 文件大?。?/td> | 561K |
| 代理商： | MC68HC05RC17DW |
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Core Timer
Core Timer Counter Register
MC68HC05RC17 — Rev. 2.0
General Release Specification
MOTOROLA
Core Timer
67
NON-DISCLOSURE
AGREEMENT
REQUIRED
8.4 Core Timer Counter Register
The timer counter register is a read-only register that contains the
current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked by the CPU clock (E/4) and can be used
for various functions, including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location, thereby simulating a 16-bit (or more) counter.
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 cycles, the power-on reset circuit is released,
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer starts counting
up from zero and normal device operation begins. When RESET is
asserted any time during operation (other than POR and low-power
reset), the counter chain is cleared.
8.5 Computer Operating Properly (COP) Reset
The COP watchdog timer function is implemented on this device by
using the output of the RTI circuit and further dividing it by eight. The
minimum COP reset rates are listed in Table 8-1. If the COP circuit times
out, an internal reset is generated and the normal reset vector is fetched.
Preventing a COP time out or clearing the COP is accomplished by
writing a 0 to bit 0 of address $3FF0. When the COP is cleared, only the
final divide-by-eight stage (output of the RTI) is cleared.
Address:
$0009
Bit 7
654321
Bit 0
Read:
D7
D6
D5
D4
D3
D2
D1
D0
Write:
Reset:
00000000
= Unimplemented
Figure 8-3. Core Timer Counter Register (CTCR)
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