- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45223 > MC68HC05RC17DW (MOTOROLA INC) 8-BIT, MROM, 2.097 MHz, MICROCONTROLLER, PDSO28 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC05RC17DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.097 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 110/128頁(yè) |
| 文件大小： | 561K |
| 代理商： | MC68HC05RC17DW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)當(dāng)前第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
NON-DISCLOSURE
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT)
General Release Specification
MC68HC05RC17 — Rev. 2.0
82
Carrier Modulator Transmitter (CMT)
MOTOROLA
9.5.3.2 Modulator Control and Status Register
The modulator control and status register (MCSR) contains the
modulator and carrier generator enable (MCGEN), interrupt enable (IE),
mode select (MODE), baseband enable (BASE), extended space
(EXSPC), and external interrupt mask (EIMSK) control bits, divide-by-
two prescaler (DIV2) bit, and the end of cycle (EOC) status bit.
EOC — End-Of-Cycle Status Flag
1 = End of modulator cycle (counter = SBUFF) has occurred
0 = Current modulation cycle in progress
EOC is set when a match occurs between the contents of the space
period register, SREG, and the down counter. This is recognized as
the end of the modulation cycle. At this time, the counter is initialized
with the (possibly new) contents of the mark period buffer, MBUFF,
and the space period register, SREG, is loaded with the (possibly new)
contents of the space period buffer, SBUFF. This flag is cleared by a
read of the MCSR followed by an access of MDR2 or MDR3. The EOC
flag is cleared by reset.
DIV2 — Divide-by-two prescaler
1 = Divide-by-two prescaler enabled
0 = Divide-by-two prescaler disabled
The divide-by-two prescaler causes the CMT to be clocked at the bus
rate when enabled; 2 x the bus rate when disabled (fosc). This bit is not
double buffered and so should not be set during a transmission.
Address:
$0014
Bit 7
654321
Bit 0
Read:
EOC
DIV2
EIMSK
EXSPC
BASE
MODE
IE
MCGEN
Write:
Reset:
00000000
= Unimplemented
Figure 9-7. Modulator Control and Status Register (MCSR)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05RC18FN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC05RC18DW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05SR3B | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP42 |
| MC68HC705SR3CP | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC705SR3CFB | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05RC8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC8DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC8FN | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC8P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05SC24 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Secure 8-bit microcomputer with EEPROM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。