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| 型號(hào)： | MC68HC05RC17DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.097 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 18/128頁(yè) |
| 文件大小： | 561K |
| 代理商： | MC68HC05RC17DW |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specications
General Release Specification
MC68HC05RC17 — Rev. 2.0
114
Electrical Specifications
MOTOROLA
12.6 DC Electrical Characteristics (5.0 Vdc)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
ILoad = 10.0 A
ILoad = –10.0 A
VOL
VOH
—
VDD –0.1
—
0.1
—
V
Output High Voltage
(ILoad –2.0 mA) Port A, Port B, Port C (1–7)
(ILoad –20.0 mA) IRO
(ILoad –4.0 mA) Port C (Bit 0)
VOH
VDD –0.8
VDD –0.7
VDD –0.8
VDD –0.2
—
V
Output Low Voltage
(ILoad = 3.0 mA) Port A, Port B, Port C (1–7)
(ILoad = 25.0 mA) IRO
(ILoad = 20.0 mA) Port C (Bit 0)
VOL
—
0.2
0.4
0.8
0.4
V
Input High Voltage
Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1
VIH
0.7xVDD
—VDD
V
Input Low Voltage
Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1
VIL
VSS
—
0.2 x VDD
V
Input Hysteresis (RESET)
VHYST
0.8
0.9
1
V
Supply Current (see Notes)
Run (fOP = 2.1 MHz)
Wait with PLL Enabled (fOP = 2.1 MHz)
Wait with PLL Disabled (fOP = 16.384 kHz)
Stop
25 oC
0 oC to +70 oC
IDD
—
3.1
1.1
39.2
0.4
4.0
1.5
60.0
10.0
20.0
mA
A
I/O Ports Hi-Z Leakage Current
Port A, Port B, Port C
IOZ
–10
—
10
A
Input Current
RESET, LPRST, IRQ, OSC1
PB0–PB7 with Pullups Enabled (VIN = 0.2 x VDD)
PB0–PB7 with Pullups Enabled (VIN = 0.7 x VDD)
IIn
–1
–100
–50
—
–496
–169
1
–700
–300
A
Capacitance
Ports (as Input or Output)
RESET, LPRST, IRQ
COut
CINT
—
12
8
pF
NOTES:
1.
VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to +70 °C, unless otherwise noted
2.
All values shown reflect average measurements.
3.
All current measurements represent the summation of current through VDD and VDDSYN supply pins.
4.
Typical values at midpoint of voltage range, 25 oC only
5.
To minimize current consumption in wait mode, disable the PLL before executing the WAIT instruction. Internal bus
speed will be that of the 32.768-kHz external frequency.
6.
Wait IDD: only core timer active
7.
Run (with PLL enabled) IDD, wait IDD (with PLL enabled): Measured using external square wave clock source
(f
OSC = 4.2 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; C
L = 20 pF on OSC2. Wait
IDD (with PLL disabled): Measured using external square wave clock source (fOSC = 33 kHz).
8.
Wait, stop IDD: Port A and port C configured as inputs; port B configured as outputs; VIL = 0.2 V; VIH = VDD –0.2 V
9.
Stop IDD is measured with OSC1 = VSS.
10. Wait IDD is affected linearly by the OSC2 capacitance.
11. Pullups are designed to be capable of pulling to VIH within 10 s for a 100 pF, 4-k load.
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