參數(shù)資料
型號(hào): MC68HC05P9AVDW
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁(yè)數(shù): 8/90頁(yè)
文件大?。?/td> 285K
代理商: MC68HC05P9AVDW
GENERAL RELEASE SPECIFICATION
MOTOROLA
GENERAL DESCRIPTION
MC68HC05P9A
1-6
Rev. 2.0
1.5.7 SDO/PB5, SDI/PB6, and SCK/PB7
Port B is a 3-bit bidirectional port. These pins are shared with the SIOP
subsystem. Refer to SECTION 7 SIMPLE SERIAL INPUT/OUTPUT PORT for a
detailed description of the SIOP. The address of the port B data register is $0001
and the data direction register is at address $0005. Reset does not affect the data
registers, but clears the data direction registers, thereby returning the ports to
inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
1.5.8 PC0 through PC2, PC3/AN3, PC4/AN2, PC5/AN1, PC6/AN0, PC7/VRH
Port C, as an 8-bit shared function port, shares ve of its pins with the A/D
converter. When the A/D converter is not enabled, PC7–PC0 form an 8-bit
general-purpose bidirectional I/O port. The contents of data direction register C
(DDRC) determine whether each pin is an input or an output.
When the A/D converter is enabled, PC7 becomes VRH, and PC6–PC3 become
AN0–AN3 (analog inputs 0–3). The values of CH1 and CH0 in the A/D status and
control register (ADSCR) select one of the four pins as the input to the A/D
converter. When the A/D converter is enabled a digital read of port C gives a
logical zero from the selected analog input pin. A digital read of port C’s remaining
pins gives their correct digital values. VRH is the positive (high) reference voltage
for the A/D converter. VSS is the negative (low) reference voltage. A reset turns off
the A/D converter and congures port C as a general-purpose I/O port. See
SECTION 10 ANALOG-TO-DIGITAL (A/D) CONVERTER.
The address of the port C data register is $0002 and the data direction register is
at address $0006. Reset does not affect the data registers, but clears the data
direction registers, thereby returning the ports to inputs. Writing a one to a DDR
bit sets the corresponding port bit to output mode. Two of the port C pins, PC0 and
PC1, have a higher current drive capability. See SECTION 13 ELECTRICAL
SPECIFICATIONS.
1.5.9 PD5 and TCAP/PD7
Port D is a 2-bit port. PD5 is I/O and TCAP/PD7 is input-only shared with the timer
input capture. The address of the port D data register is $0003 and the data
direction register is at address $0007. Reset does not affect the data registers, but
clears the data direction registers, thereby returning the ports to inputs. Writing a
one to a DDR bit sets the corresponding port bit to output mode. The TCAP/PD7
pin controls the input capture feature for the on-chip programmable timer. This pin
can be read at any time even if the TCAP function is enabled.
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