參數(shù)資料
型號(hào)： MC68HC05P8EVS
廠商： Motorola, Inc.
英文描述： HCMOS MICROCONTROLLER UNIT
中文描述： HCMOS微控制器
文件頁數(shù)： 76/82頁
文件大小： 327K
代理商： MC68HC05P8EVS
MOTOROLA
11-10
ELECTRICAL SPECIFICATIONS
MC68HC705J2
Rev. 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Figure 11-8. Power-On Reset Timing
Figure 11-9. External Reset Timing
OSC1 PIN
VDD
4064 tcyc
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
INTERNAL
DATA
BUS
0FFF
0FFE
0FFE
0FFE
0FFE
NEW
PCL
NEW
PCH
0FFE
0FFE
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode.
3. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode.
POR THRESHOLD (TYPICALLY 1–2 V)
tVDDR
1
1
1
2
2
2
2
2
2
3
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
RESET
NOTES:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
3. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode.
4. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode.
tRL
NEW PC
DUMMY
INTERNAL
DATA
BUS
NEW PC
OP
CODE
0FFF
NEW
PCL
0FFE
NEW
PCH
0FFE
0FFE
0FFE3
3
3
3
4
2
1
1
1
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