參數(shù)資料
型號(hào)： MC68HC05P8EVS
廠(chǎng)商： Motorola, Inc.
英文描述： HCMOS MICROCONTROLLER UNIT
中文描述： HCMOS微控制器
文件頁(yè)數(shù)： 44/82頁(yè)
文件大小： 327K
代理商： MC68HC05P8EVS
MOTOROLA
7-2
TIMER
MC68HC705J2
Rev. 2
1
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7.1 Timer Counter Register (TCR)
A 15-stage ripple counter is the core of the timer. The value of the first eight stages
is readable at any time from the read-only timer counter register shown in
Figure
7-2
.
Figure 7-2. Timer Counter Register (TCR)
Power-on clears the entire counter chain and begins clocking the counter. After
4064 cycles of the internal clock, the power-on reset circuit is released, clearing the
counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage makes timer interrupts
possible every 1024 internal clock cycles.
7.2 Timer Control and Status Register (TCSR)
Timer interrupt flags, timer interrupt enable bits, and real-time interrupt rate select
bits are in the read/write timer control and status register.
Figure 7-3. Timer Control and Status Register (TCSR)
TCR —
Timer Counter Register
$0009
Bit 7
6
5
4
3
2
1
Bit 0
RESET
0
0
0
0
0
0
0
0
TCSR —
Timer Control and Status Register
$0008
Bit 7
TOF
0
6
5
4
3
0
0
2
0
0
1
Bit 0
RT0
1
RTIF
0
TOIE
0
RTIE
0
RT1
1
RESET
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