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參數資料
| 型號： | MC68HC05P4ADW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數： | 27/72頁 |
| 文件大?。?/td> | 400K |
| 代理商： | MC68HC05P4ADW |
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SIOP Registers
MC68HC05P4A Data Sheet, Rev. 7.1
Freescale Semiconductor
33
MSTR — Master Mode Bit
When set, this bit configures the SIOP for master mode. This means that the transmission is initiated
by a write to the data register and the SCK pin becomes an output providing a synchronous data clock
at a fixed rate of E (bus clock) divided by four. While the device is in master mode, the SDO and SDI
pins do not change function. These pins behave exactly as they would in slave mode. Reset clears this
bit and configures the SIOP for slave operation. MSTR may be set at any time regardless of the state
of SPE. Clearing MSTR will abort any transmission in progress.
7.3.2 SIOP Status Register
This register is located at address $000B and contains only two bits.
SPIF — Serial Peripheral Interface Flag Bit
This bit is set upon occurrence of the last rising clock edge and indicates that a data transfer has taken
place. It has no effect on any further transmissions and can be ignored without problem. SPIF is
cleared by reading the SSR with SPIF set followed by a read or write of the serial data register. If it is
cleared before the last edge of the next byte, it will be set again. Reset clears this bit.
DCOL — Data Collision Bit
This is a read-only status bit which indicates that an invalid access to the data register has been made.
This can occur any time after the first falling edge of SCK and before SPIF is set. A read or write of the
data register during this time will result in invalid data being transmitted or received.
NOTE
DCOL is cleared by reading the status register with SPIF set followed by a
read or write of the data register. If the last part of the clearing sequence is
done after another transmission has been started, DCOL will be set again.
If the DCOL bit is set and the SPIF is not set, clearing the DCOL requires
turning the SIOP off then turning it back on. Reset also clears this bit.
Address:
$000B
Bit 7
654321
Bit 0
Read:
SPIF
DCOL
000000
Write:
Reset:
00000000
= Unimplemented
Figure 7-4. SIOP Status Register (SSR)
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PDF描述 |
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| MC68HC05P6VS | 8-BIT, 2.1 MHz, MICROCONTROLLER, CDIP28 |
| MC68HC05P6CS | 8-BIT, 2.1 MHz, MICROCONTROLLER, CDIP28 |
| MC68HC05P6VP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05P6CDW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05P6DW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68HC05P4DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P4P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P6 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P6_1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05P8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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