參數(shù)資料
型號(hào): MC68HC05P4ACDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 39/102頁
文件大小: 1085K
代理商: MC68HC05P4ACDW
Interrupts
External Interrupt
MC68HC05P4A — Rev. 7.0
Technical Data
MOTOROLA
Interrupts
41
Figure 4-2. IRQ Function Block Diagram
NOTE:
When the edge- and level-sensitive mask option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed to avoid the
processor re-entering the IRQ service routine.
The IRQ pin is one source of an IRQ interrupt and a mask option can
also enable the port A pins (PA0–PA7) to act as other IRQ interrupt
sources. These sources are all combined into a single ORing function to
be latched by the IRQ latch.
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge
of the IRQ pin or a port A pin if port A interrupts have been enabled. If
edge-only sensitivity is chosen by a mask option, only the IRQ latch
output can activate a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to:
1. Falling edge on the IRQ pin with all enabled port A interrupt pins
at a high level
2. Falling edge on any enabled port A interrupt pin with all other
enabled port A interrupt pins and the IRQ pin at a high level
IRQ
LATCH
R
VDD
IRQ PIN
MASK OPTION
(IRQ LEVEL)
TO IRQ
PROCESSING
IN CPU
TO BIH & BIL
INSTRUCTION
SENSING
RST
IRQ VECTOR FETCH
PA7
DDRA7
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
PA7 IRQ INHIBIT
(MASK OPTION)
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