參數(shù)資料
型號: MC68HC05P4ACDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 35/102頁
文件大?。?/td> 1085K
代理商: MC68HC05P4ACDW
Interrupts
Technical Data
MC68HC05P4A — Rev. 7.0
38
Interrupts
MOTOROLA
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-bit
state.
Table 4-1 lists vector addresses for all interrupts including reset.
4.3 Hardware Controlled Interrupt Sequence
RESET, STOP, and WAIT are not interrupts in the strictest sense.
However, they are acted upon in a similar manner. Flowcharts for
hardware interrupts are shown in Figure 4-1 and for STOP and WAIT in
Figure 6-1. STOP/WAIT Flowchart. A discussion is provided here.
1. RESET — A low input on the RESET input pin causes the
program to vector to its starting address, which is specified by
the contents of memory locations $1FFE and $1FFF. The I bit in
the condition code register also is set. Much of the MCU is
configured to a known state during this type of reset as described
Table 4-1. Vector Address for Interrupts and Reset
Register
Flag
Name
Interrupts
CPU
Interrupt
Vector Address
N/A
Reset
RESET
$1FFE–$1FFF
N/A
Software
SWI
$1FFC–$1FFD
N/A
External interrupt
IRQ
$1FFA–$1FFB
TSR
ICF
Timer input capture
TIMER
$1FF8–$1FF9
TSR
OCF
Timer output capture
TIMER
$1FF8–$1FF9
TSR
TOF
Timer overflow
TIMER
$1FF8–$1FF9
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