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參數(shù)資料
| 型號(hào)： | MC68HC05L1FU |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 47/102頁(yè) |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC05L1FU |
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MC68HC05L1
MOTOROLA
5-13
PROGRAMMABLE TIMER
5
Figure 5-4 Timer State Timing Diagram for Output Compare
Figure 5-5 Timer State Diagram for Timer Overow
INTERNAL
PROCESSOR
CLOCK
T00
T01
T10
T11
COUNTER
(16 BIT)
INTERNAL
TIMER
CLOCKS
$F455
$F456
$F457
$F458
$F459
Note 1
Note 2
$F457
CPU writes $F457
OUTPUT COMPARE
REGISTER
COMPARE REGISTER
OUTPUT COMPARE
Flag and TCMP1, 2
Note:
1. The CPU write to the compare registers may take place at any time, but a compare only occurs at
the timer state T01. Thus a 4-cycle difference may exist between the write to the compare register
and the actual compare.
2. The output compare ag is set at the timer state T11 that follows the comparison match ($F547 in
this example).
LATCH
Note 1
INTERNAL
PROCESSOR
CLOCK
T00
T01
T10
T11
COUNTER
(16 BIT)
INTERNAL
TIMER
CLOCKS
$FFFE
$FFFF
$0000
$0001
$0002
Note:
TIMER
OVERFLOW
FLAG (TOF)
The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000).
It is cleared by a read of the timer status register during the internal processor
clock high time followed by a read of the counter low register.
TPG
47
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